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CY8C21434-24LTXIT

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Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY8C21434-24LTXIT

Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

CY8C21434-24LTXIT from Infineon Cypress Semicon, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0[1] bidirectional Analog column mux input and integrating input; every port pin also supports digital I/O and connection to the common analog bus.
2 P2[7] bidirectional Port 2 bit 7 general-purpose I/O that connects to the analog mux bus.
3 P2[5] bidirectional Port 2 bit 5 general-purpose I/O that connects to the analog mux bus.
4 P2[3] bidirectional Port 2 bit 3 general-purpose I/O that connects to the analog mux bus.
5 P2[1] bidirectional Port 2 bit 1 general-purpose I/O that connects to the analog mux bus.
6 P3[3] bidirectional Port 3 bit 3 general-purpose I/O that connects to the analog mux bus; this pin is P3[3] on the CY8C21434 (on the CY8C21634 it is the SMP pin).
7 P3[1] bidirectional Port 3 bit 1 general-purpose I/O that connects to the analog mux bus; this pin is P3[1] on the CY8C21434 (on the CY8C21634 it is VSS).
8 P1[7] bidirectional Port 1 bit 7 general-purpose I/O, also the I2C SCL line.
9 P1[5] bidirectional Port 1 bit 5 general-purpose I/O, also the I2C SDA line.
10 P1[3] bidirectional Port 1 bit 3 general-purpose I/O that connects to the analog mux bus.
11 P1[1] bidirectional Port 1 bit 1, also I2C SCL and ISSP-SCLK; ISSP pins are not high Z at POR.
12 VSS power_in Ground connection; all VSS pins should be brought out to one common GND plane.
13 P1[0] bidirectional Port 1 bit 0, also I2C SDA and ISSP-SDATA; ISSP pins are not high Z at POR.
14 P1[2] bidirectional Port 1 bit 2 general-purpose I/O that connects to the analog mux bus.
15 P1[4] bidirectional Port 1 bit 4, also the optional external clock input (EXTCLK).
16 P1[6] bidirectional Port 1 bit 6 general-purpose I/O that connects to the analog mux bus.
17 XRES input Active high external reset with internal pull-down.
18 P3[0] bidirectional Port 3 bit 0 general-purpose I/O that connects to the analog mux bus.
19 P3[2] bidirectional Port 3 bit 2 general-purpose I/O that connects to the analog mux bus.
20 P2[0] bidirectional Port 2 bit 0 general-purpose I/O that connects to the analog mux bus.
21 P2[2] bidirectional Port 2 bit 2 general-purpose I/O that connects to the analog mux bus.
22 P2[4] bidirectional Port 2 bit 4 general-purpose I/O that connects to the analog mux bus.
23 P2[6] bidirectional Port 2 bit 6 general-purpose I/O that connects to the analog mux bus.
24 P0[0] bidirectional Analog column mux input; every port pin also supports digital I/O.
25 P0[2] bidirectional Analog column mux input; every port pin also supports digital I/O.
26 P0[4] bidirectional Analog column mux input; every port pin also supports digital I/O.
27 P0[6] bidirectional Analog column mux input; every port pin also supports digital I/O.
28 VDD power_in Supply voltage.
29 P0[7] bidirectional Analog column mux input; every port pin also supports digital I/O.
30 P0[5] bidirectional Analog column mux input; every port pin also supports digital I/O.
31 P0[3] bidirectional Analog column mux input and integrating input; every port pin also supports digital I/O.
32 VSS power_in Ground connection; all VSS pins should be brought out to one common GND plane.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 25 100 °C Higher storage temperatures reduce data retention time 20
Ambient temperature with power applied TA -40 85 °C 20
Supply voltage on VDD relative to VSS VDD -0.5 6 V 20
Maximum current into any port pin IMIO -25 50 mA 20
Electrostatic discharge voltage ESD 2000 V Human body model ESD 20
Latch-up current LU 200 mA 20
Junction temperature TJ -40 100 °C Temperature rise from ambient to junction is package specific (Table 29) 20
Ambient temperature (operating) TA -40 85 °C 20
Supply voltage VDD 2.4 5.25 V 21
Supply current, IMO = 24 MHz IDD 3 4 mA VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, 48 MHz disabled 21
Supply current, IMO = 6 MHz using SLIMO mode IDD3 1.2 2 mA VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled 21
Supply current, IMO = 6 MHz using SLIMO mode (2.7 V) IDD27 1.1 1.5 mA VDD = 2.55 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled 21
Sleep (mode) current with POR, LVD, sleep timer, WDT and internal slow oscillator active (mid temperature range) ISB27 2.6 4 µA VDD = 2.55 V, 0 °C ≤ TA ≤ 40 °C 21
Sleep (mode) current with POR, LVD, Sleep Timer, WDT and internal slow oscillator active ISB 2.8 5 µA VDD = 3.3 V, -40 °C ≤ TA ≤ 85 °C 21
Reference voltage (Bandgap) VREF 1.28 1.3 1.32 V VDD = 3.0 V to 5.25 V; trimmed for appropriate VDD 21
Reference voltage (Bandgap) at 2.4 V to 3.0 V VREF27 1.16 1.3 1.33 V VDD = 2.4 V to 3.0 V; trimmed for appropriate VDD 21
Pull-up resistor (5 V / 3.3 V) RPU 4 5.6 8 k 22
Pull-down resistor (5 V / 3.3 V) RPD 4 5.6 8 k 22
Low output level (5 V / 3.3 V) VOL 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads) 22
High level source current (5 V / 3.3 V) IOH 10 mA VOH = VDD, 1.0 V 22
Low level sink current (5 V / 3.3 V) IOL 25 mA VOL = 0.75 V 22
Input low level (5 V / 3.3 V) VIL 0.8 V VDD = 3.0 to 5.25 V 22
Input high level (5 V / 3.3 V) VIH 2.1 V VDD = 3.0 to 5.25 V 22
Capacitive load on pins as input (5 V / 3.3 V) CIN 3.5 10 pF Package and pin dependent; Temp = 25 °C 22
Capacitive load on pins as output (5 V / 3.3 V) COUT 3.5 10 pF Package and pin dependent; Temp = 25 °C 22
Low output level (2.7 V) VOL 0.75 V IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA maximum combined IOL budget) 22
High level source current (2.7 V) IOH 2.5 mA VOH = VDD, 0.4 V 22
Low level sink current (2.7 V) IOL 10 mA VOL = 0.75 V 22
Input low level (2.7 V) VIL 0.75 V VDD = 2.4 to 3.0 V 22
Input high level (2.7 V) VIH 2 V VDD = 2.4 to 3.0 V 22
Capacitive load on pins as input (2.7 V) CIN 3.5 10 pF Package and pin dependent; Temp = 25 °C 22
Capacitive load on pins as output (2.7 V) COUT 3.5 10 pF Package and pin dependent; Temp = 25 °C 22
VDD for programming and erase VDDP 4.5 5 5.5 V Applies to functional requirements of external programmer tools 26
Low VDD for verify VDDLV 2.4 2.5 2.6 V Applies to functional requirements of external programmer tools 26
High VDD for verify VDDHV 5.1 5.2 5.3 V Applies to functional requirements of external programmer tools 26
Supply voltage for flash write operation VDDIWRITE 2.7 5.25 V Applies when the device is executing internal flash writes 26
Supply current during programming or verify IDDP 5 25 mA 26
Input low voltage during programming or verify VILP 0.8 V 26
Input high voltage during programming or verify VIHP 2.2 V 26
Flash endurance (per block) FlashENPB 50000 Erase/write cycles per block Guaranteed only if flash operates within one voltage range 26
Flash endurance (total) FlashENT 1.8e+06 Erase/write cycles 26
Flash data retention FlashDR 10 Years 26
IMO frequency for 24 MHz FIMO24 23.4 24 24.6 MHz Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO mode = 0 27
IMO frequency for 6 MHz FIMO6 5.52 6 6.48 MHz Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO mode = 1 27
CPU frequency (5 V nominal) FCPU1 0.091 24 24.6 MHz 4.75 V < VDD < 5.25 V; 24 MHz only for SLIMO mode = 0 27
Digital PSoC block frequency (5 V nominal) FBLK5 0 48 49.2 MHz 4.75 V < VDD < 5.25 V 27
ILO frequency F32K1 15 32 64 kHz 27
24 MHz duty cycle DC24M 40 50 60 % 27
48 MHz output frequency Fout48M 46.8 48 49.2 MHz Trimmed; using factory trim values 27
Maximum frequency of signal on row input or row output FMAX 12.3 MHz 27
Power supply slew rate SRPOWER_UP 250 V/ms VDD slew rate during power-up 27
Time from end of POR to CPU executing code tPOWERUP 16 100 ms Power-up from 0 V 27
IMO frequency for 12 MHz (2.7 V) FIMO12 11.04 120 12.96 MHz Trimmed for 2.7 V operation using factory trim values; SLIMO mode = 1 28
CPU frequency (2.7 V nominal) FCPU1 0.093 3 3.15 MHz 2.4 V < VDD < 3.0 V; 12 MHz only for SLIMO mode = 0 28
Frequency with CPU clock divide by 1 (3.3 V external clock) FOSCEXT 0.093 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3 V; CPU clock divider set to 1 32
Frequency with CPU clock divide by 2 or greater (3.3 V external clock) FOSCEXT 0.186 24.6 MHz If external clock is greater than 12 MHz, CPU clock divider must be 2 or greater 32
Frequency of SCLK (AC programming) FSCLK 0 8 MHz 33
Flash block erase + flash block write time (hot) TPROGRAM_HOT 100 ms 0 °C ≤ Tj ≤ 100 °C 33
Flash block erase + flash block write time (cold) TPROGRAM_COLD 200 ms -40 °C ≤ Tj ≤ 0 °C 33

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 7

CAD (KiCad official)

  • Symbol: CY8C21434-24LTXIT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cy8c21434-24ltxit-etched.step / cy8c21434-24ltxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c21434-24ltxit.step / cy8c21434-24ltxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (60 pp, sha256 7db3409733a84c2e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF