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CY8C21345-24SXI
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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CY8C21345-24SXI
Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28
CY8C21345-24SXI from Cypress Semicon, in a SOIC-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0[7] | bidirectional | GPIO port 0 bit 7 with analog input and analog mux right (MR) connection; integration capacitor for MR. |
| 2 | P0[5] | bidirectional | GPIO port 0 bit 5 with analog input and analog mux left (ML) connection; integration capacitor for ML. |
| 3 | P0[3] | bidirectional | GPIO port 0 bit 3 with analog input and analog mux left (ML) connection. |
| 4 | P0[1] | bidirectional | GPIO port 0 bit 1 with analog input and analog mux left (ML) connection. |
| 5 | P2[7] | bidirectional | GPIO port 2 bit 7 with analog input and ML connection; to compare column 0. |
| 6 | P2[5] | bidirectional | GPIO port 2 bit 5 with ML connection; optional ADC external Vref. |
| 7 | P2[3] | bidirectional | GPIO port 2 bit 3 with analog mux left (ML) connection. |
| 8 | P2[1] | bidirectional | GPIO port 2 bit 1 with analog mux left (ML) connection. |
| 9 | Vss | power_in | Ground connection; all Vss pins should be brought out to one common GND plane. |
| 10 | P1[7] | bidirectional | GPIO port 1 bit 7 with ML connection; I2C serial clock (SCL). |
| 11 | P1[5] | bidirectional | GPIO port 1 bit 5 with ML connection; I2C serial data (SDA). |
| 12 | P1[3] | bidirectional | GPIO port 1 bit 3 with analog mux left (ML) connection. |
| 13 | P1[1] | bidirectional | GPIO port 1 bit 1 with ML connection; I2C SCL and ISSP-SCLK, pulled down to ground in resistive zero drive mode after POR/XRES if ISSP not used. |
| 14 | Vss | power_in | Ground connection; all Vss pins should be brought out to one common GND plane. |
| 15 | P1[0] | bidirectional | GPIO port 1 bit 0 with MR connection; I2C SCL/SDATA and ISSP-SDATA, pulled down to ground in resistive zero drive mode after POR/XRES if ISSP not used. |
| 16 | P1[2] | bidirectional | GPIO port 1 bit 2 with analog mux right (MR) connection. |
| 17 | P1[4] | bidirectional | GPIO port 1 bit 4 with MR connection; optional external clock input (EXT-CLK). |
| 18 | P1[6] | bidirectional | GPIO port 1 bit 6 with analog mux right (MR) connection. |
| 19 | XRES | input | Active high pin reset with internal pull down. |
| 20 | P2[0] | bidirectional | GPIO port 2 bit 0 with analog mux right (MR) connection. |
| 21 | P2[2] | bidirectional | GPIO port 2 bit 2 with analog mux right (MR) connection. |
| 22 | P2[4] | bidirectional | GPIO port 2 bit 4 with analog mux right (MR) connection. |
| 23 | P2[6] | bidirectional | GPIO port 2 bit 6 with analog input and MR connection; to compare column 1. |
| 24 | P0[0] | bidirectional | GPIO port 0 bit 0 with analog input and analog mux right (MR) connection. |
| 25 | P0[2] | bidirectional | GPIO port 2 bit 2 of port 0 with analog input and analog mux right (MR) connection. |
| 26 | P0[4] | bidirectional | GPIO port 0 bit 4 with analog input and analog mux right (MR) connection. |
| 27 | P0[6] | bidirectional | GPIO port 0 bit 6 with analog input and analog mux right (MR) connection. |
| 28 | Vdd | power_in | Supply voltage; device operating range is 3.0 V to 5.25 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SOIC-28 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 28 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | The emulator consists of a base unit that connects to the PC | 6 |
CAD (KiCad official)
- Symbol:
CY8C21345-24SXI - Footprint:
Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm - 3D model: SOIC-28 (KiCad packages3D, STEP)
- 3D model files:
cy8c21345-24sxi-etched.step/cy8c21345-24sxi-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c21345-24sxi.step/cy8c21345-24sxi.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (40 pp, sha256
d84b5190da05c378, retrieved 2026-10-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CY8C21345-24SXI
**Cypress Semicon** · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28
CY8C21345-24SXI from Cypress Semicon, in a SOIC-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0[7] | bidirectional | GPIO port 0 bit 7 with analog input and analog mux right (MR) connection; integration capacitor for MR. |
| 2 | P0[5] | bidirectional | GPIO port 0 bit 5 with analog input and analog mux left (ML) connection; integration capacitor for ML. |
| 3 | P0[3] | bidirectional | GPIO port 0 bit 3 with analog input and analog mux left (ML) connection. |
| 4 | P0[1] | bidirectional | GPIO port 0 bit 1 with analog input and analog mux left (ML) connection. |
| 5 | P2[7] | bidirectional | GPIO port 2 bit 7 with analog input and ML connection; to compare column 0. |
| 6 | P2[5] | bidirectional | GPIO port 2 bit 5 with ML connection; optional ADC external Vref. |
| 7 | P2[3] | bidirectional | GPIO port 2 bit 3 with analog mux left (ML) connection. |
| 8 | P2[1] | bidirectional | GPIO port 2 bit 1 with analog mux left (ML) connection. |
| 9 | Vss | power_in | Ground connection; all Vss pins should be brought out to one common GND plane. |
| 10 | P1[7] | bidirectional | GPIO port 1 bit 7 with ML connection; I2C serial clock (SCL). |
| 11 | P1[5] | bidirectional | GPIO port 1 bit 5 with ML connection; I2C serial data (SDA). |
| 12 | P1[3] | bidirectional | GPIO port 1 bit 3 with analog mux left (ML) connection. |
| 13 | P1[1] | bidirectional | GPIO port 1 bit 1 with ML connection; I2C SCL and ISSP-SCLK, pulled down to ground in resistive zero drive mode after POR/XRES if ISSP not used. |
| 14 | Vss | power_in | Ground connection; all Vss pins should be brought out to one common GND plane. |
| 15 | P1[0] | bidirectional | GPIO port 1 bit 0 with MR connection; I2C SCL/SDATA and ISSP-SDATA, pulled down to ground in resistive zero drive mode after POR/XRES if ISSP not used. |
| 16 | P1[2] | bidirectional | GPIO port 1 bit 2 with analog mux right (MR) connection. |
| 17 | P1[4] | bidirectional | GPIO port 1 bit 4 with MR connection; optional external clock input (EXT-CLK). |
| 18 | P1[6] | bidirectional | GPIO port 1 bit 6 with analog mux right (MR) connection. |
| 19 | XRES | input | Active high pin reset with internal pull down. |
| 20 | P2[0] | bidirectional | GPIO port 2 bit 0 with analog mux right (MR) connection. |
| 21 | P2[2] | bidirectional | GPIO port 2 bit 2 with analog mux right (MR) connection. |
| 22 | P2[4] | bidirectional | GPIO port 2 bit 4 with analog mux right (MR) connection. |
| 23 | P2[6] | bidirectional | GPIO port 2 bit 6 with analog input and MR connection; to compare column 1. |
| 24 | P0[0] | bidirectional | GPIO port 0 bit 0 with analog input and analog mux right (MR) connection. |
| 25 | P0[2] | bidirectional | GPIO port 2 bit 2 of port 0 with analog input and analog mux right (MR) connection. |
| 26 | P0[4] | bidirectional | GPIO port 0 bit 4 with analog input and analog mux right (MR) connection. |
| 27 | P0[6] | bidirectional | GPIO port 0 bit 6 with analog input and analog mux right (MR) connection. |
| 28 | Vdd | power_in | Supply voltage; device operating range is 3.0 V to 5.25 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SOIC-28 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 28 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | The emulator consists of a base unit that connects to the PC | 6 |
## CAD (KiCad official)
- Symbol: `CY8C21345-24SXI`
- Footprint: `Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm`
- 3D model: SOIC-28 (KiCad packages3D, STEP)
- 3D model files: `cy8c21345-24sxi-etched.step` / `cy8c21345-24sxi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy8c21345-24sxi.step` / `cy8c21345-24sxi.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Cypress Semicon datasheet](https://www.infineon.com/dgdl/Infineon-CY8C21345_CY8C22345_CY8C22545_PSoC_Programmable_System-on-Chip-DataSheet-v24_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec6d23f3d51&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files) (40 pp, sha256 `d84b5190da05c378`, retrieved 2026-10-24, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cy8c21345-24sxi-datasheet.pdf)