component

CY7C68014A-56PVXC

Public Made by Adom

by adom

Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), SSOP-56. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy7c68014a-56pvxcfactory-2.0.0extractor-text

Verified CY7C68014A-56PVXC

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 56 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY7C68014A-56PVXC · SSOP-56 · 56 pins
  • ✓copper: 56 copper pads, none touching another net
  • ✓datasheet: all 56 pin names found in the 75-page datasheet
  • ✓distributor: lcsc C2948520, digikey 448-CY7C68014A-56PVXC-ND, mouser 727-CY768014A-56PVXC
  • ✓family: SSOP-56_7.5x18.5mm_P0.635mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-e1vd94bz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 56 pins = 56 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 56 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy7c68014a-56pvxc.kicad_sym✓ cy7c68014a-56pvxc.kicad_mod✓ cy7c68014a-56pvxc.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cy7c68014a-56pvxc / README.md
History Download
Ray Publish 0.1.0 584652d

CY7C68014A-56PVXC

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · SSOP-56

CY7C68014A-56PVXC from Cypress Semicon, in a SSOP-56. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD5/FD13 bidirectional Port D bit 5 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[13], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
2 PD6/FD14 bidirectional Port D bit 6 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[14], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
3 PD7/FD15 bidirectional Port D bit 7 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[15], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
4 GND power_in Ground.
5 CLKOUT tri_state CLKOUT is a 12-, 24- or 48-MHz clock phase-locked to the 24-MHz input clock, defaulting to 12 MHz, and may be three-stated by setting CPUCS.1 = 1.
6 VCC power_in Connect to the 3.3-V power source.
7 GND power_in Ground.
8 RDY0/SLRD input RDY0 is a GPIF input signal, and SLRD is the input-only read strobe for the slave FIFOs with programmable polarity (FIFOPINPOLAR.3).
9 RDY1/SLWR input RDY1 is a GPIF input signal, and SLWR is the input-only write strobe for the slave FIFOs with programmable polarity (FIFOPINPOLAR.2).
10 AVCC power_in Analog VCC; connect to the 3.3 V power source to power the analog section of the chip.
11 XTALOUT output Crystal output; connect to a 24-MHz parallel-resonant fundamental mode crystal and load capacitor to GND, or leave open if XTALIN is driven by an external clock.
12 XTALIN input Crystal input; connect to a 24-MHz parallel-resonant fundamental mode crystal and load capacitor to GND, or drive with a 3.3-V square wave.
13 AGND power_in Analog ground; connect to ground with as short a path as possible.
14 AVCC power_in Analog VCC; connect to the 3.3 V power source to power the analog section of the chip.
15 DPLUS bidirectional USB D+ signal; connect to the USB D+ signal.
16 DMINUS bidirectional USB D- signal; connect to the USB D- signal.
17 AGND power_in Analog ground; connect to ground with as short a path as possible.
18 VCC power_in Connect to the 3.3-V power source.
19 GND power_in Ground.
20 IFCLK bidirectional Interface clock for synchronously clocking data into or out of the slave FIFOs, also a timing reference for slave FIFO control signals and GPIF; may be inverted by IFCONFIG.4.
21 RESERVED input Reserved; connect to ground.
22 SCL bidirectional Clock for the I2C interface; connect to VCC with a 2.2-k resistor even if no I2C peripheral is attached.
23 SDA bidirectional Data for the I2C compatible interface; connect to VCC with a 2.2-k resistor even if no I2C compatible peripheral is attached.
24 VCC power_in Connect to the 3.3-V power source.
25 PB0/FD0 bidirectional Port B bit 0 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[0], selected by IFCONFIG[1..0].
26 PB1/FD1 bidirectional Port B bit 1 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[1], selected by IFCONFIG[1..0].
27 PB2/FD2 bidirectional Port B bit 2 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[2], selected by IFCONFIG[1..0].
28 PB3/FD3 bidirectional Port B bit 3 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[3], selected by IFCONFIG[1..0].
29 PB4/FD4 bidirectional Port B bit 4 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[4], selected by IFCONFIG[1..0].
30 PB5/FD5 bidirectional Port B bit 5 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[5], selected by IFCONFIG[1..0].
31 PB6/FD6 bidirectional Port B bit 6 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[6], selected by IFCONFIG[1..0].
32 PB7/FD7 bidirectional Port B bit 7 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[7], selected by IFCONFIG[1..0].
33 GND power_in Ground.
34 VCC power_in Connect to the 3.3-V power source.
35 GND power_in Ground.
36 CTL0/FLAGA tri_state CTL0 is a GPIF control output, and FLAGA is a programmable slave-FIFO output status flag; the function is selected by IFCONFIG[1..0].
37 CTL1/FLAGB tri_state CTL1 is a GPIF control output, and FLAGB is a programmable slave-FIFO output status flag; the function is selected by IFCONFIG[1..0].
38 CTL2/FLAGC tri_state CTL2 is a GPIF control output, and FLAGC is a programmable slave-FIFO output status flag; the function is selected by IFCONFIG[1..0].
39 VCC power_in Connect to the 3.3-V power source.
40 PA0/INT0# bidirectional PA0 is a bidirectional I/O port pin, and INT0# is the active-LOW 8051 INT0 interrupt input, edge-triggered (IT0 = 1) or level-triggered (IT0 = 0), selected by PORTACFG.0.
41 PA1/INT1# bidirectional PA1 is a bidirectional I/O port pin, and INT1# is the active-LOW 8051 INT1 interrupt input, edge-triggered (IT1 = 1) or level-triggered (IT1 = 0), selected by PORTACFG.1.
42 PA2/SLOE bidirectional PA2 is a bidirectional I/O port pin, and SLOE is an input-only output enable for the slave FIFOs with programmable polarity (FIFOPINPOLAR.4).
43 PA3/WU2 bidirectional PA3 is a bidirectional I/O port pin, and WU2 is an alternate USB wakeup source enabled by WU2EN (WAKEUP.1) with polarity set by WU2POL (WAKEUP.4).
44 PA4/FIFOADR0 bidirectional PA4 is a bidirectional I/O port pin, and FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
45 PA5/FIFOADR1 bidirectional PA5 is a bidirectional I/O port pin, and FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
46 PA6/PKTEND bidirectional PA6 is a bidirectional I/O port pin, and PKTEND is an input used to commit FIFO packet data to the endpoint, with polarity programmable via FIFOPINPOLAR.5.
47 PA7/FLAGD/SLCS# bidirectional PA7 is a bidirectional I/O port pin, FLAGD is a programmable slave-FIFO output status flag, and SLCS# gates all other slave FIFO enable/strobes.
48 GND power_in Ground.
49 RESET# input Active LOW reset; resets the entire chip.
50 VCC power_in Connect to the 3.3-V power source.
51 WAKEUP input USB wakeup; if the 8051 is in suspend, asserting this pin starts the oscillator and interrupts the 8051 to exit suspend mode, with programmable polarity (WAKEUP.4).
52 PD0/FD8 bidirectional Port D bit 0 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[8], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
53 PD1/FD9 bidirectional Port D bit 1 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[9], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
54 PD2/FD10 bidirectional Port D bit 2 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[10], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
55 PD3/FD11 bidirectional Port D bit 3 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[11], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).
56 PD4/FD12 bidirectional Port D bit 4 is a bidirectional I/O pin that is multiplexed with FIFO/GPIF data bus bit FD[12], selected by IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SSOP-56
Category Single Chip Microcomputer/Microcontroller
Pins 56

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.3 3.6 V 43
Input HIGH voltage VIH 2 5.25 V 43
Input LOW voltage VIL -0.5 0.8 V 43
Crystal input HIGH voltage VIH_X 2 5.25 V 43
Crystal input LOW voltage VIL_X -0.5 0.8 V 43
Input leakage current II -10 10 µA 0< VIN < VCC 43
Output voltage HIGH VOH 2.4 V IOUT = 4 mA 43
Output LOW voltage VOL 0.4 V IOUT = -4 mA 43
Output current HIGH IOH 4 mA 43
Output current LOW IOL 4 mA 43
Input pin capacitance CIN 10 pF Except D+/D- 43
Input pin capacitance D+/D- CIN 15 pF D+/D- 43
Suspend current, disconnected (CY7C68014/CY7C68016) ISUSP 100 150 µA CY7C68014/CY7C68016 Disconnected; measured at Max VCC, 25 °C (note 28) 43
Supply current, 8051 running, connected to USB HS ICC 50 85 mA 8051 running, connected to USB HS 43
Supply current, 8051 running, connected to USB FS ICC 35 65 mA 8051 running, connected to USB FS 43
Reset time after valid power TRESET 5 ms VCC min = 3.0 V 43
Pin reset after powered on 200 µs Pin reset after powered on 43
Ambient temperature under bias, Commercial TA 0 70 °C Commercial 42
Supply voltage (operating conditions) VCC 3 3.6 V 42
Oscillator frequency tolerance FOSC -100 100 ppm 24 MHz crystal, parallel resonant 42
Storage temperature -65 150 °C 42
Ambient temperature with power supplied (Commercial) 0 70 °C Commercial 42
Supply voltage to ground potential -0.5 4 V 42
DC input voltage to any input pin 5.25 V 42
DC voltage applied to outputs in high Z state -0.5 V Upper limit printed as VCC + 0.5 V 42
Power dissipation 300 mW 42
Static discharge voltage 2000 V Printed >2000 V 42
Max output current, per I/O port 10 mA Per I/O port 42
Maximum junction temperature 125 °C 42
Crystal load capacitor tolerance C1, C2 -5 5 % External crystal load capacitors, 12-pF (5% tolerance) 6
Crystal load capacitor C1, C2 12 pF External crystal load capacitors, Figure 1 6
Oscillator frequency FOSC 24 MHz Parallel resonant crystal 42
Thermal resistance junction to case, 56 SSOP Jc 24.4 °C/W Ambient temperature 70 °C 42
Thermal resistance junction to ambient, 56 SSOP Ja 47.7 °C/W Ambient temperature 70 °C 42

CAD (KiCad official)

  • Symbol: CY7C68014A-56PVXC
  • Footprint: Package_SO:SSOP-56_7.5x18.5mm_P0.635mm
  • 3D model: SSOP-56 (KiCad packages3D, STEP)
  • 3D model files: cy7c68014a-56pvxc-etched.step / cy7c68014a-56pvxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c68014a-56pvxc.step / cy7c68014a-56pvxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (75 pp, sha256 67d39521d4c85939, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF