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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-56(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY7C68014A-56LTXC

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-56(8x8)

CY7C68014A-56LTXC from Cypress Semicon, in a QFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RDY0/SLRD	input	RDY0 is a GPIF input signal, and SLRD is the input-only slave FIFO read strobe with programmable polarity (FIFOPINPOLAR.3).
2	RDY1/SLWR	input	RDY1 is a GPIF input signal, and SLWR is the input-only slave FIFO write strobe with programmable polarity (FIFOPINPOLAR.2).
3	AVCC	power_in	Analog VCC; connect to the 3.3 V power source to supply the analog section of the chip.
4	XTALOUT	output	Crystal output; connect to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND, or leave open if XTALIN is driven externally.
5	XTALIN	input	Crystal input; connect to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND, or drive with a 3.3-V square wave at 24 MHz.
6	AGND	power_in	Analog ground; connect to ground with as short a path as possible.
7	AVCC	power_in	Analog VCC; connect to the 3.3 V power source to supply the analog section of the chip.
8	DPLUS	bidirectional	USB D+ signal; connect to the USB D+ signal.
9	DMINUS	bidirectional	USB D- signal; connect to the USB D- signal.
10	AGND	power_in	Analog ground; connect to ground with as short a path as possible.
11	VCC	power_in	VCC; connect to the 3.3-V power source.
12	GND	power_in	Ground.
13	IFCLK	bidirectional	Interface clock for synchronously clocking data into or out of the slave FIFOs, also a timing reference for slave FIFO control signals and GPIF; it can be configured to output 30/48 MHz when internal clocking is used.
14	Reserved	input	Reserved pin; connect to ground.
15	SCL	bidirectional	Clock for the I2C interface (open-drain); connect to VCC with a 2.2-k resistor, even if no I2C peripheral is attached.
16	SDA	bidirectional	Data for the I2C compatible interface (open-drain); connect to VCC with a 2.2-k resistor, even if no I2C compatible peripheral is attached.
17	VCC	power_in	VCC; connect to the 3.3-V power source.
18	PB0/FD0	bidirectional	Bidirectional I/O port pin PB0, multiplexed with FD[0], the bidirectional FIFO/GPIF data bus.
19	PB1/FD1	bidirectional	Bidirectional I/O port pin PB1, multiplexed with FD[1], the bidirectional FIFO/GPIF data bus.
20	PB2/FD2	bidirectional	Bidirectional I/O port pin PB2, multiplexed with FD[2], the bidirectional FIFO/GPIF data bus.
21	PB3/FD3	bidirectional	Bidirectional I/O port pin PB3, multiplexed with FD[3], the bidirectional FIFO/GPIF data bus.
22	PB4/FD4	bidirectional	Bidirectional I/O port pin PB4, multiplexed with FD[4], the bidirectional FIFO/GPIF data bus.
23	PB5/FD5	bidirectional	Bidirectional I/O port pin PB5, multiplexed with FD[5], the bidirectional FIFO/GPIF data bus.
24	PB6/FD6	bidirectional	Bidirectional I/O port pin PB6, multiplexed with FD[6], the bidirectional FIFO/GPIF data bus.
25	PB7/FD7	bidirectional	Bidirectional I/O port pin PB7, multiplexed with FD[7], the bidirectional FIFO/GPIF data bus.
26	GND	power_in	Ground.
27	VCC	power_in	VCC; connect to the 3.3-V power source.
28	GND	power_in	Ground.
29	CTL0/FLAGA	tri_state	GPIF control output CTL0, or programmable slave FIFO output status flag FLAGA, selected by IFCONFIG[1:0].
30	CTL1/FLAGB	tri_state	GPIF control output CTL1, or programmable slave FIFO output status flag FLAGB, selected by IFCONFIG[1:0].
31	CTL2/FLAGC	tri_state	GPIF control output CTL2, or programmable slave FIFO output status flag FLAGC, selected by IFCONFIG[1:0].
32	VCC	power_in	VCC; connect to the 3.3-V power source.
33	PA0/INT0#	bidirectional	Bidirectional I/O port pin PA0, multiplexed with INT0#, the active-LOW 8051 INT0 interrupt input.
34	PA1/INT1#	bidirectional	Bidirectional I/O port pin PA1, multiplexed with INT1#, the active-LOW 8051 INT1 interrupt input.
35	PA2/SLOE	bidirectional	Bidirectional I/O port pin PA2, multiplexed with SLOE, an input-only slave FIFO output enable with programmable polarity.
36	PA3/WU2	bidirectional	Bidirectional I/O port pin PA3, multiplexed with WU2, an alternate USB wakeup source enabled by WU2EN and polarity set by WU2POL.
37	PA4/FIFOADR0	bidirectional	Bidirectional I/O port pin PA4, multiplexed with FIFOADR0, an input-only address select for the slave FIFOs.
38	PA5/FIFOADR1	bidirectional	Bidirectional I/O port pin PA5, multiplexed with FIFOADR1, an input-only address select for the slave FIFOs.
39	PA6/PKTEND	bidirectional	Bidirectional I/O port pin PA6, multiplexed with PKTEND, an input used to commit FIFO packet data to the endpoint with programmable polarity.
40	PA7/FLAGD/SLCS#	bidirectional	Bidirectional I/O port pin PA7, multiplexed with FLAGD (programmable slave FIFO status flag) or SLCS#, which gates all other slave FIFO enable/strobes.
41	GND	power_in	Ground.
42	RESET#	input	Active LOW reset that resets the entire chip.
43	VCC	power_in	VCC; connect to the 3.3-V power source.
44	WAKEUP	input	USB wakeup input; when the 8051 is in suspend, asserting this pin starts the oscillator and interrupts the 8051 to exit suspend, with programmable polarity (WAKEUP.4).
45	PD0/FD8	bidirectional	Bidirectional I/O port pin PD0, multiplexed with FD[8], the bidirectional FIFO/GPIF data bus.
46	PD1/FD9	bidirectional	Bidirectional I/O port pin PD1, multiplexed with FD[9], the bidirectional FIFO/GPIF data bus.
47	PD2/FD10	bidirectional	Bidirectional I/O port pin PD2, multiplexed with FD[10], the bidirectional FIFO/GPIF data bus.
48	PD3/FD11	bidirectional	Bidirectional I/O port pin PD3, multiplexed with FD[11], the bidirectional FIFO/GPIF data bus.
49	PD4/FD12	bidirectional	Bidirectional I/O port pin PD4, multiplexed with FD[12], the bidirectional FIFO/GPIF data bus.
50	PD5/FD13	bidirectional	Bidirectional I/O port pin PD5, multiplexed with FD[13], the bidirectional FIFO/GPIF data bus.
51	PD6/FD14	bidirectional	Bidirectional I/O port pin PD6, multiplexed with FD[14], the bidirectional FIFO/GPIF data bus.
52	PD7/FD15	bidirectional	Bidirectional I/O port pin PD7, multiplexed with FD[15], the bidirectional FIFO/GPIF data bus.
53	GND	power_in	Ground.
54	CLKOUT	tri_state	CLKOUT: 12-, 24- or 48-MHz clock phase-locked to the 24-MHz input clock; the 8051 may three-state this output by setting CPUCS.1 = 1.
55	VCC	power_in	VCC; connect to the 3.3-V power source.
56	GND	power_in	Ground.
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	QFN-56(8x8)
Category	Single Chip Microcomputer/Microcontroller
Pins	57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	3	3.3	3.6	V		43
Input HIGH voltage	VIH	2		5.25	V		43
Input LOW voltage	VIL	-0.5		0.8	V		43
Crystal input HIGH voltage	VIH_X	2		5.25	V		43
Crystal input LOW voltage	VIL_X	-0.5		0.8	V		43
Input leakage current	II	-10		10	µA	0< VIN < VCC	43
Output voltage HIGH	VOH	2.4			V	IOUT = 4 mA	43
Output LOW voltage	VOL			0.4	V	IOUT = -4 mA	43
Output current HIGH	IOH			4	mA		43
Output current LOW	IOL			4	mA		43
Input pin capacitance (except D+/D-)	CIN			10	pF	Except D+/D-	43
Input pin capacitance D+/D-	CIN			15	pF	D+/D-	43
Suspend current (Disconnected)	ISUSP		100	150	µA	CY7C68014/CY7C68016 Disconnected; measured at max VCC, 25 °C	43
Suspend current (Connected)	ISUSP		300	380	µA	Connected; measured at max VCC, 25 °C	43
Supply current, USB HS	ICC		50	85	mA	8051 running, connected to USB HS	43
Supply current, USB FS	ICC		35	65	mA	8051 running, connected to USB FS	43
Reset time after valid power	TRESET	5			ms	VCC min = 3.0 V	43
Pin reset after powered on	TRESET	200			µs		43
VCC Ramp Up		200			µs	0 to 3.3 V	43
Storage temperature		-65		150	°C		42
Ambient temperature with power supplied (Commercial)		0		70	°C	Commercial	42
Supply voltage to ground potential		-0.5		4	V		42
DC input voltage to any input pin				5.25	V		42
DC voltage applied to outputs in high Z state		-0.5			V	max VCC + 0.5 V	42
Power dissipation				300	mW		42
Static discharge voltage		2000			V	>2000 V	42
Max output current, per I/O port				10	mA		42
Operating ambient temperature (Commercial)	TA	0		70	°C	Commercial, ambient under bias	42
Supply voltage		3		3.6	V		42
Ground voltage			0		V		42
Oscillator or crystal frequency	FOSC		24		MHz	± 100 ppm, parallel resonant	42
Maximum junction temperature				125	°C		42
Junction to case thermal resistance, 56 QFN	θJC		10.6		°C/W	Ambient 70 °C	42
Junction to ambient thermal resistance, 56 QFN	θJA		25.2		°C/W	Ambient 70 °C	42

CAD (KiCad official)

Symbol: CY7C68014A-56LTXC
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56(8x8) (KiCad packages3D, STEP)
3D model files: cy7c68014a-56ltxc-etched.step / cy7c68014a-56ltxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c68014a-56ltxc.step / cy7c68014a-56ltxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (75 pp, sha256 67d39521d4c85939, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# CY7C68014A-56LTXC

**Cypress Semicon** · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-56(8x8)

CY7C68014A-56LTXC from Cypress Semicon, in a QFN-56(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RDY0/SLRD | input | RDY0 is a GPIF input signal, and SLRD is the input-only slave FIFO read strobe with programmable polarity (FIFOPINPOLAR.3). |
| 2 | RDY1/SLWR | input | RDY1 is a GPIF input signal, and SLWR is the input-only slave FIFO write strobe with programmable polarity (FIFOPINPOLAR.2). |
| 3 | AVCC | power_in | Analog VCC; connect to the 3.3 V power source to supply the analog section of the chip. |
| 4 | XTALOUT | output | Crystal output; connect to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND, or leave open if XTALIN is driven externally. |
| 5 | XTALIN | input | Crystal input; connect to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND, or drive with a 3.3-V square wave at 24 MHz. |
| 6 | AGND | power_in | Analog ground; connect to ground with as short a path as possible. |
| 7 | AVCC | power_in | Analog VCC; connect to the 3.3 V power source to supply the analog section of the chip. |
| 8 | DPLUS | bidirectional | USB D+ signal; connect to the USB D+ signal. |
| 9 | DMINUS | bidirectional | USB D- signal; connect to the USB D- signal. |
| 10 | AGND | power_in | Analog ground; connect to ground with as short a path as possible. |
| 11 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 12 | GND | power_in | Ground. |
| 13 | IFCLK | bidirectional | Interface clock for synchronously clocking data into or out of the slave FIFOs, also a timing reference for slave FIFO control signals and GPIF; it can be configured to output 30/48 MHz when internal clocking is used. |
| 14 | Reserved | input | Reserved pin; connect to ground. |
| 15 | SCL | bidirectional | Clock for the I2C interface (open-drain); connect to VCC with a 2.2-k resistor, even if no I2C peripheral is attached. |
| 16 | SDA | bidirectional | Data for the I2C compatible interface (open-drain); connect to VCC with a 2.2-k resistor, even if no I2C compatible peripheral is attached. |
| 17 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 18 | PB0/FD0 | bidirectional | Bidirectional I/O port pin PB0, multiplexed with FD[0], the bidirectional FIFO/GPIF data bus. |
| 19 | PB1/FD1 | bidirectional | Bidirectional I/O port pin PB1, multiplexed with FD[1], the bidirectional FIFO/GPIF data bus. |
| 20 | PB2/FD2 | bidirectional | Bidirectional I/O port pin PB2, multiplexed with FD[2], the bidirectional FIFO/GPIF data bus. |
| 21 | PB3/FD3 | bidirectional | Bidirectional I/O port pin PB3, multiplexed with FD[3], the bidirectional FIFO/GPIF data bus. |
| 22 | PB4/FD4 | bidirectional | Bidirectional I/O port pin PB4, multiplexed with FD[4], the bidirectional FIFO/GPIF data bus. |
| 23 | PB5/FD5 | bidirectional | Bidirectional I/O port pin PB5, multiplexed with FD[5], the bidirectional FIFO/GPIF data bus. |
| 24 | PB6/FD6 | bidirectional | Bidirectional I/O port pin PB6, multiplexed with FD[6], the bidirectional FIFO/GPIF data bus. |
| 25 | PB7/FD7 | bidirectional | Bidirectional I/O port pin PB7, multiplexed with FD[7], the bidirectional FIFO/GPIF data bus. |
| 26 | GND | power_in | Ground. |
| 27 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 28 | GND | power_in | Ground. |
| 29 | CTL0/FLAGA | tri_state | GPIF control output CTL0, or programmable slave FIFO output status flag FLAGA, selected by IFCONFIG[1:0]. |
| 30 | CTL1/FLAGB | tri_state | GPIF control output CTL1, or programmable slave FIFO output status flag FLAGB, selected by IFCONFIG[1:0]. |
| 31 | CTL2/FLAGC | tri_state | GPIF control output CTL2, or programmable slave FIFO output status flag FLAGC, selected by IFCONFIG[1:0]. |
| 32 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 33 | PA0/INT0# | bidirectional | Bidirectional I/O port pin PA0, multiplexed with INT0#, the active-LOW 8051 INT0 interrupt input. |
| 34 | PA1/INT1# | bidirectional | Bidirectional I/O port pin PA1, multiplexed with INT1#, the active-LOW 8051 INT1 interrupt input. |
| 35 | PA2/SLOE | bidirectional | Bidirectional I/O port pin PA2, multiplexed with SLOE, an input-only slave FIFO output enable with programmable polarity. |
| 36 | PA3/WU2 | bidirectional | Bidirectional I/O port pin PA3, multiplexed with WU2, an alternate USB wakeup source enabled by WU2EN and polarity set by WU2POL. |
| 37 | PA4/FIFOADR0 | bidirectional | Bidirectional I/O port pin PA4, multiplexed with FIFOADR0, an input-only address select for the slave FIFOs. |
| 38 | PA5/FIFOADR1 | bidirectional | Bidirectional I/O port pin PA5, multiplexed with FIFOADR1, an input-only address select for the slave FIFOs. |
| 39 | PA6/PKTEND | bidirectional | Bidirectional I/O port pin PA6, multiplexed with PKTEND, an input used to commit FIFO packet data to the endpoint with programmable polarity. |
| 40 | PA7/FLAGD/SLCS# | bidirectional | Bidirectional I/O port pin PA7, multiplexed with FLAGD (programmable slave FIFO status flag) or SLCS#, which gates all other slave FIFO enable/strobes. |
| 41 | GND | power_in | Ground. |
| 42 | RESET# | input | Active LOW reset that resets the entire chip. |
| 43 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 44 | WAKEUP | input | USB wakeup input; when the 8051 is in suspend, asserting this pin starts the oscillator and interrupts the 8051 to exit suspend, with programmable polarity (WAKEUP.4). |
| 45 | PD0/FD8 | bidirectional | Bidirectional I/O port pin PD0, multiplexed with FD[8], the bidirectional FIFO/GPIF data bus. |
| 46 | PD1/FD9 | bidirectional | Bidirectional I/O port pin PD1, multiplexed with FD[9], the bidirectional FIFO/GPIF data bus. |
| 47 | PD2/FD10 | bidirectional | Bidirectional I/O port pin PD2, multiplexed with FD[10], the bidirectional FIFO/GPIF data bus. |
| 48 | PD3/FD11 | bidirectional | Bidirectional I/O port pin PD3, multiplexed with FD[11], the bidirectional FIFO/GPIF data bus. |
| 49 | PD4/FD12 | bidirectional | Bidirectional I/O port pin PD4, multiplexed with FD[12], the bidirectional FIFO/GPIF data bus. |
| 50 | PD5/FD13 | bidirectional | Bidirectional I/O port pin PD5, multiplexed with FD[13], the bidirectional FIFO/GPIF data bus. |
| 51 | PD6/FD14 | bidirectional | Bidirectional I/O port pin PD6, multiplexed with FD[14], the bidirectional FIFO/GPIF data bus. |
| 52 | PD7/FD15 | bidirectional | Bidirectional I/O port pin PD7, multiplexed with FD[15], the bidirectional FIFO/GPIF data bus. |
| 53 | GND | power_in | Ground. |
| 54 | CLKOUT | tri_state | CLKOUT: 12-, 24- or 48-MHz clock phase-locked to the 24-MHz input clock; the 8051 may three-state this output by setting CPUCS.1 = 1. |
| 55 | VCC | power_in | VCC; connect to the 3.3-V power source. |
| 56 | GND | power_in | Ground. |
| 57 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | QFN-56(8x8) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 57 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 3 | 3.3 | 3.6 | V |  | 43 |
| Input HIGH voltage | VIH | 2 |  | 5.25 | V |  | 43 |
| Input LOW voltage | VIL | -0.5 |  | 0.8 | V |  | 43 |
| Crystal input HIGH voltage | VIH_X | 2 |  | 5.25 | V |  | 43 |
| Crystal input LOW voltage | VIL_X | -0.5 |  | 0.8 | V |  | 43 |
| Input leakage current | II | -10 |  | 10 | µA | 0< VIN < VCC | 43 |
| Output voltage HIGH | VOH | 2.4 |  |  | V | IOUT = 4 mA | 43 |
| Output LOW voltage | VOL |  |  | 0.4 | V | IOUT = -4 mA | 43 |
| Output current HIGH | IOH |  |  | 4 | mA |  | 43 |
| Output current LOW | IOL |  |  | 4 | mA |  | 43 |
| Input pin capacitance (except D+/D-) | CIN |  |  | 10 | pF | Except D+/D- | 43 |
| Input pin capacitance D+/D- | CIN |  |  | 15 | pF | D+/D- | 43 |
| Suspend current (Disconnected) | ISUSP |  | 100 | 150 | µA | CY7C68014/CY7C68016 Disconnected; measured at max VCC, 25 °C | 43 |
| Suspend current (Connected) | ISUSP |  | 300 | 380 | µA | Connected; measured at max VCC, 25 °C | 43 |
| Supply current, USB HS | ICC |  | 50 | 85 | mA | 8051 running, connected to USB HS | 43 |
| Supply current, USB FS | ICC |  | 35 | 65 | mA | 8051 running, connected to USB FS | 43 |
| Reset time after valid power | TRESET | 5 |  |  | ms | VCC min = 3.0 V | 43 |
| Pin reset after powered on | TRESET | 200 |  |  | µs |  | 43 |
| VCC Ramp Up |  | 200 |  |  | µs | 0 to 3.3 V | 43 |
| Storage temperature |  | -65 |  | 150 | °C |  | 42 |
| Ambient temperature with power supplied (Commercial) |  | 0 |  | 70 | °C | Commercial | 42 |
| Supply voltage to ground potential |  | -0.5 |  | 4 | V |  | 42 |
| DC input voltage to any input pin |  |  |  | 5.25 | V |  | 42 |
| DC voltage applied to outputs in high Z state |  | -0.5 |  |  | V | max VCC + 0.5 V | 42 |
| Power dissipation |  |  |  | 300 | mW |  | 42 |
| Static discharge voltage |  | 2000 |  |  | V | >2000 V | 42 |
| Max output current, per I/O port |  |  |  | 10 | mA |  | 42 |
| Operating ambient temperature (Commercial) | TA | 0 |  | 70 | °C | Commercial, ambient under bias | 42 |
| Supply voltage |  | 3 |  | 3.6 | V |  | 42 |
| Ground voltage |  |  | 0 |  | V |  | 42 |
| Oscillator or crystal frequency | FOSC |  | 24 |  | MHz | ± 100 ppm, parallel resonant | 42 |
| Maximum junction temperature |  |  |  | 125 | °C |  | 42 |
| Junction to case thermal resistance, 56 QFN | θJC |  | 10.6 |  | °C/W | Ambient 70 °C | 42 |
| Junction to ambient thermal resistance, 56 QFN | θJA |  | 25.2 |  | °C/W | Ambient 70 °C | 42 |

## CAD (KiCad official)

- Symbol: `CY7C68014A-56LTXC`
- Footprint: `Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm`
- 3D model: QFN-56(8x8) (KiCad packages3D, STEP)
- 3D model files: `cy7c68014a-56ltxc-etched.step` / `cy7c68014a-56ltxc-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy7c68014a-56ltxc.step` / `cy7c68014a-56ltxc.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Cypress Semicon datasheet](https://www.infineon.com/dgdl/Infineon-CY7C68013A_CY7C68014A_CY7C68015A_CY7C68016A_EZ-USB_FX2LP_USB_Microcontroller_High-Speed_USB_Peripheral_Controller-DataSheet-v31_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec9f7974252&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files&redirId=File_1_3_1556) (75 pp, sha256 `67d39521d4c85939`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cy7c68014a-56ltxc-datasheet.pdf)

CY7C68014A-56LTXC

Changed since verified CY7C68014A-56LTXC

Verification log 1 record

CY7C68014A-56LTXC

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance