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CY7C68013A-56PVXC

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Cypress Semicon CYPRESS, SSOP-56-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY7C68013A-56PVXC

Cypress Semicon · CYPRESS · SSOP-56-300mil

CY7C68013A-56PVXC from Cypress Semicon, in a SSOP-56-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PD5/FD13 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[13] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
2 PD6/FD14 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[14] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
3 PD7/FD15 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[15] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
4 GND power_in Ground connection for the device.
5 CLKOUT tri_state CLKOUT outputs a 12-, 24- or 48-MHz clock phase-locked to the 24-MHz input clock, and may be three-stated by setting CPUCS.1 = 1.
6 VCC power_in Connect to the 3.3-V power source.
7 GND power_in Ground connection for the device.
8 RDY0/SLRD input RDY0 is a GPIF input signal, multiplexed with SLRD, the input-only read strobe with programmable polarity for the slave FIFOs.
9 RDY1/SLWR input RDY1 is a GPIF input signal, multiplexed with SLWR, the input-only write strobe with programmable polarity for the slave FIFOs.
10 AVCC power_in Analog VCC, connect to the 3.3-V power source to supply the analog section of the chip.
11 XTALOUT output Crystal output for a 24-MHz parallel-resonant fundamental mode crystal and load capacitor to GND, left open if an external clock drives XTALIN.
12 XTALIN input Crystal input for a 24-MHz parallel-resonant fundamental mode crystal, or a 3.3-V square wave at 24 MHz from an external source.
13 AGND power_in Analog ground, connect to ground with as short a path as possible.
14 AVCC power_in Analog VCC, connect to the 3.3-V power source to supply the analog section of the chip.
15 DPLUS bidirectional USB D+ signal, connect to the USB D+ signal.
16 DMINUS bidirectional USB D- signal, connect to the USB D- signal.
17 AGND power_in Analog ground, connect to ground with as short a path as possible.
18 VCC power_in Connect to the 3.3-V power source.
19 GND power_in Ground connection for the device.
20 IFCLK bidirectional Interface clock for synchronously clocking data into or out of the slave FIFOs, which can output 30/48 MHz when internal clocking is used.
21 RESERVED input Reserved pin, connect to ground.
22 SCL bidirectional Clock for the I2C interface, connect to VCC with a 2.2-k resistor even if no I2C peripheral is attached.
23 SDA bidirectional Data for the I2C compatible interface, connect to VCC with a 2.2-k resistor even if no I2C compatible peripheral is attached.
24 VCC power_in Connect to the 3.3-V power source.
25 PB0/FD0 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[0] under the IFCONFIG[1..0] settings.
26 PB1/FD1 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[1] under the IFCONFIG[1..0] settings.
27 PB2/FD2 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[2] under the IFCONFIG[1..0] settings.
28 PB3/FD3 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[3] under the IFCONFIG[1..0] settings.
29 PB4/FD4 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[4] under the IFCONFIG[1..0] settings.
30 PB5/FD5 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[5] under the IFCONFIG[1..0] settings.
31 PB6/FD6 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[6] under the IFCONFIG[1..0] settings.
32 PB7/FD7 bidirectional Port B bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[7] under the IFCONFIG[1..0] settings.
33 GND power_in Ground connection for the device.
34 VCC power_in Connect to the 3.3-V power source.
35 GND power_in Ground connection for the device.
36 CTL0/FLAGA tri_state GPIF control output CTL0, multiplexed with FLAGA, a programmable slave-FIFO output status flag.
37 CTL1/FLAGB tri_state GPIF control output CTL1, multiplexed with FLAGB, a programmable slave-FIFO output status flag.
38 CTL2/FLAGC tri_state GPIF control output CTL2, multiplexed with FLAGC, a programmable slave-FIFO output status flag.
39 VCC power_in Connect to the 3.3-V power source.
40 PA0/INT0# bidirectional Port A bidirectional I/O pin, multiplexed with INT0#, the active-LOW 8051 INT0 interrupt input.
41 PA1/INT1# bidirectional Port A bidirectional I/O pin, multiplexed with INT1#, the active-LOW 8051 INT1 interrupt input.
42 PA2/SLOE bidirectional Port A bidirectional I/O pin, multiplexed with SLOE, an input-only output enable with programmable polarity for the slave FIFOs.
43 PA3/WU2 bidirectional Port A bidirectional I/O pin, multiplexed with WU2, an alternate source for USB wakeup with programmable polarity.
44 PA4/FIFOADR0 bidirectional Port A bidirectional I/O pin, multiplexed with FIFOADR0, an input-only address select for the slave FIFOs.
45 PA5/FIFOADR1 bidirectional Port A bidirectional I/O pin, multiplexed with FIFOADR1, an input-only address select for the slave FIFOs.
46 PA6/PKTEND bidirectional Port A bidirectional I/O pin, multiplexed with PKTEND, an input used to commit FIFO packet data to the endpoint.
47 PA7/FLAGD/SLCS# bidirectional Port A bidirectional I/O pin, multiplexed with FLAGD, a programmable slave-FIFO output status flag, or with SLCS#, which gates all other slave FIFO enable/strobes.
48 GND power_in Ground connection for the device.
49 RESET# input Active LOW reset that resets the entire chip.
50 VCC power_in Connect to the 3.3-V power source.
51 WAKEUP input USB wakeup input that starts the oscillator and interrupts the 8051 when suspended, and holding it asserted inhibits suspend.
52 PD0/FD8 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[8] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
53 PD1/FD9 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[9] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
54 PD2/FD10 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[10] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
55 PD3/FD11 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[11] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.
56 PD4/FD12 bidirectional Port D bidirectional I/O pin, multiplexed with FIFO/GPIF data bus bit FD[12] under the IFCONFIG[1..0] and EPxFIFOCFG.0 settings.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SSOP-56-300mil
Category Embedded Processors & Controllers
Pins 56

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.3 3.6 V , 43
Input HIGH voltage VIH 2 5.25 V , 43
Input LOW voltage VIL -0.5 0.8 V , 43
Crystal input HIGH voltage VIH_X 2 5.25 V , 43
Crystal input LOW voltage VIL_X -0.5 0.8 V , 43
Input leakage current II -10 10 A 0< VIN < VCC 43
Output voltage HIGH VOH 2.4 V IOUT = 4 mA 43
Output LOW voltage VOL 0.4 V IOUT = -4 mA 43
Output current HIGH IOH 4 mA , 43
Output current LOW IOL 4 mA , 43
Input pin capacitance CIN 10 pF Except D+/D- 43
Input pin capacitance D+/D- CIN 15 pF D+/D- 43
Suspend current ISUSP 300 380 A Connected 43
Suspend current (CY7C68013/CY7C68015) ISUSP 0.5 1.2 mA Connected 43
Suspend current (CY7C68013/CY7C68015) ISUSP 0.3 1 mA Disconnected 43
Supply current ICC 50 85 mA 8051 running, connected to USB HS 43
Supply current ICC 35 65 mA 8051 running, connected to USB FS 43
VCC ramp up 200 s 0 to 3.3 V 43
Reset time after valid power TRESET 5 ms VCC min = 3.0 V 43
Pin reset after powered on 200 s , 43
Storage temperature -65 150 °C , 42
Ambient temperature with power supplied (Commercial) 0 70 °C , 42
Supply voltage to ground potential -0.5 4 V , 42
DC input voltage to any input pin 5.25 V , 42
DC voltage applied to outputs in high Z state -0.5 V VCC + 0.5 V 42
Power dissipation 300 mW , 42
Static discharge voltage 2000 V printed as >2000 V 42
Max output current, per I/O port 10 mA , 42
Ambient temperature under bias (Commercial) TA 0 70 °C , 42
Supply voltage 3 3.6 V , 42
Oscillator or crystal frequency tolerance FOSC -100 100 ppm 24 MHz, parallel resonant 42
Maximum junction temperature 125 °C , 42
Junction to case thermal resistance, 56 SSOP Jc 24.4 °C/W Ambient 70 °C 42
Junction to ambient thermal resistance, 56 SSOP Ja 47.7 °C/W Ambient 70 °C 42

CAD (KiCad official)

  • Symbol: CY7C68013A-56PVXC
  • Footprint: Package_SO:SSOP-56_7.5x18.5mm_P0.635mm
  • 3D model: SSOP-56-300mil (KiCad packages3D, STEP)
  • 3D model files: cy7c68013a-56pvxc-etched.step / cy7c68013a-56pvxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c68013a-56pvxc.step / cy7c68013a-56pvxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (75 pp, sha256 67d39521d4c85939, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF