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CY7C68013A-128AXC

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Cypress Semicon CYPRESS, QFP-128(14x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY7C68013A-128AXC

Cypress Semicon · CYPRESS · QFP-128(14x20)

CY7C68013A-128AXC from Cypress Semicon, in a QFP-128(14x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKOUT output 12-, 24- or 48-MHz clock phase-locked to the 24-MHz input clock, defaults to 12 MHz and can be three-stated by setting CPUCS.1 = 1.
2 VCC power_in VCC, connect to the 3.3-V power source.
3 GND power_in Ground.
4 RDY0/SLRD input RDY0 is a GPIF input signal; SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs, selected by IFCONFIG[1..0].
5 RDY1/SLWR input RDY1 is a GPIF input signal; SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs, selected by IFCONFIG[1..0].
6 RDY2 input RDY2 is a GPIF input signal.
7 RDY3 input RDY3 is a GPIF input signal.
8 RDY4 input RDY4 is a GPIF input signal.
9 RDY5 input RDY5 is a GPIF input signal.
10 AVCC power_in Analog VCC, connect to the 3.3 V power source; powers the analog section of the chip.
11 XTALOUT output Crystal output, connect to a 24-MHz parallel-resonant fundamental mode crystal and load capacitor to GND; leave open if an external clock drives XTALIN.
12 XTALIN input Crystal input, connect to a 24-MHz parallel-resonant fundamental mode crystal and load capacitor to GND, or drive with a 3.3-V 24-MHz square wave.
13 AGND power_in Analog ground, connect to ground with as short a path as possible.
14 NC unconnected No connect; this pin must be left open.
15 NC unconnected No connect; this pin must be left open.
16 NC unconnected No connect; this pin must be left open.
17 AVCC power_in Analog VCC, connect to the 3.3 V power source; powers the analog section of the chip.
18 DPLUS bidirectional USB D+ signal, connect to the USB D+ line.
19 DMINUS bidirectional USB D- signal, connect to the USB D- line.
20 AGND power_in Analog ground, connect to ground with as short a path as possible.
21 A11 output 8051 address bus bit 11, driven at all times and reflecting the internal address when addressing internal RAM.
22 A12 output 8051 address bus bit 12, driven at all times and reflecting the internal address when addressing internal RAM.
23 A13 output 8051 address bus bit 13, driven at all times and reflecting the internal address when addressing internal RAM.
24 A14 output 8051 address bus bit 14, driven at all times and reflecting the internal address when addressing internal RAM.
25 A15 output 8051 address bus bit 15, driven at all times and reflecting the internal address when addressing internal RAM.
26 VCC power_in VCC, connect to the 3.3-V power source.
27 GND power_in Ground.
28 INT4 input 8051 INT4 interrupt request input, edge-sensitive, active HIGH.
29 T0 input Active HIGH T0 input for 8051 Timer0, used as the Timer0 input when C/T0 is 1.
30 T1 input Active HIGH T1 input for 8051 Timer1, used as the Timer1 input when C/T1 is 1.
31 T2 input Active HIGH T2 input to 8051 Timer2, used as the Timer2 input when C/T2 = 1.
32 IFCLK bidirectional Interface clock for synchronously clocking data into or out of the slave FIFOs and timing reference for GPIF; can output 30/48 MHz when internal clocking is used and can be inverted via IFCONFIG.4.
33 RESERVED input Reserved, connect to ground.
34 BKPT output Breakpoint output that goes active HIGH when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled (BPEN = 1).
35 EA input External Access, selects whether the 8051 fetches code at 0x0000-0x3FFF from internal RAM (EA = 0) or external memory (EA = 1).
36 SCL bidirectional Open-drain clock for the I2C interface; connect to VCC with a 2.2-kOhm resistor even if no I2C peripheral is attached.
37 SDA bidirectional Open-drain data for the I2C interface; connect to VCC with a 2.2-kOhm resistor even if no I2C peripheral is attached.
38 OE# output Active LOW output enable for external memory.
39 PSEN# output Program Store Enable, active LOW signal indicating an 8051 code fetch from external memory.
40 RD# output Active LOW read strobe output for external memory.
41 WR# output Active LOW write strobe output for external memory.
42 CS# output Active LOW chip select for external memory.
43 VCC power_in VCC, connect to the 3.3-V power source.
44 PB0/FD0 bidirectional Port B bit 0 I/O or bidirectional FIFO/GPIF data bus bit 0, selected by IFCONFIG[1..0].
45 PB1/FD1 bidirectional Port B bit 1 I/O or bidirectional FIFO/GPIF data bus bit 1, selected by IFCONFIG[1..0].
46 PB2/FD2 bidirectional Port B bit 2 I/O or bidirectional FIFO/GPIF data bus bit 2, selected by IFCONFIG[1..0].
47 PB3/FD3 bidirectional Port B bit 3 I/O or bidirectional FIFO/GPIF data bus bit 3, selected by IFCONFIG[1..0].
48 VCC power_in VCC, connect to the 3.3-V power source.
49 GND power_in Ground.
50 TXD0 output Active HIGH TXD0 output from 8051 UART0, providing the output clock in sync mode and output data in async mode.
51 RXD0 input Active HIGH RXD0 input to 8051 UART0, providing data to the UART in all modes.
52 TXD1 output Active HIGH output from 8051 UART1, providing the output clock in sync mode and output data in async mode.
53 RXD1 input Active HIGH input for 8051 UART1, providing data to the UART in all modes.
54 PB4/FD4 bidirectional Port B bit 4 I/O or bidirectional FIFO/GPIF data bus bit 4, selected by IFCONFIG[1..0].
55 PB5/FD5 bidirectional Port B bit 5 I/O or bidirectional FIFO/GPIF data bus bit 5, selected by IFCONFIG[1..0].
56 PB6/FD6 bidirectional Port B bit 6 I/O or bidirectional FIFO/GPIF data bus bit 6, selected by IFCONFIG[1..0].
57 PB7/FD7 bidirectional Port B bit 7 I/O or bidirectional FIFO/GPIF data bus bit 7, selected by IFCONFIG[1..0].
58 GND power_in Ground.
59 D0 bidirectional 8051 data bus bit 0 for external program and data memory, high impedance when inactive and driven LOW in suspend.
60 D1 bidirectional 8051 data bus bit 1 for external program and data memory, high impedance when inactive and driven LOW in suspend.
61 D2 bidirectional 8051 data bus bit 2 for external program and data memory, high impedance when inactive and driven LOW in suspend.
62 D3 bidirectional 8051 data bus bit 3 for external program and data memory, high impedance when inactive and driven LOW in suspend.
63 D4 bidirectional 8051 data bus bit 4 for external program and data memory, high impedance when inactive and driven LOW in suspend.
64 VCC power_in VCC, connect to the 3.3-V power source.
65 GND power_in Ground.
66 CTL3 output CTL3 is a GPIF control output.
67 CTL4 output CTL4 is a GPIF control output.
68 VCC power_in VCC, connect to the 3.3-V power source.
69 CTL0/FLAGA output CTL0 is a GPIF control output or FLAGA is a programmable slave-FIFO status flag, selected by IFCONFIG[1..0].
70 CTL1/FLAGB output CTL1 is a GPIF control output or FLAGB is a programmable slave-FIFO status flag defaulting to FULL, selected by IFCONFIG[1..0].
71 CTL2/FLAGC output CTL2 is a GPIF control output or FLAGC is a programmable slave-FIFO status flag defaulting to EMPTY, selected by IFCONFIG[1..0].
72 PC0/GPIFADR0 bidirectional Port C bit 0 I/O or GPIF address output 0, selected by PORTCCFG.0.
73 PC1/GPIFADR1 bidirectional Port C bit 1 I/O or GPIF address output 1, selected by PORTCCFG.1.
74 PC2/GPIFADR2 bidirectional Port C bit 2 I/O or GPIF address output 2, selected by PORTCCFG.2.
75 PC3/GPIFADR3 bidirectional Port C bit 3 I/O or GPIF address output 3, selected by PORTCCFG.3.
76 PC4/GPIFADR4 bidirectional Port C bit 4 I/O or GPIF address output 4, selected by PORTCCFG.4.
77 PC5/GPIFADR5 bidirectional Port C bit 5 I/O or GPIF address output 5, selected by PORTCCFG.5.
78 PC6/GPIFADR6 bidirectional Port C bit 6 I/O or GPIF address output 6, selected by PORTCCFG.6.
79 PC7/GPIFADR7 bidirectional Port C bit 7 I/O or GPIF address output 7, selected by PORTCCFG.7.
80 GND power_in Ground.
81 VCC power_in VCC, connect to the 3.3-V power source.
82 PA0/INT0# bidirectional Port A bit 0 I/O or active-LOW 8051 INT0 interrupt input (edge- or level-triggered), selected by PORTACFG.0.
83 PA1/INT1# bidirectional Port A bit 1 I/O or active-LOW 8051 INT1 interrupt input (edge- or level-triggered), selected by PORTACFG.1.
84 PA2/SLOE bidirectional Port A bit 2 I/O or input-only slave FIFO output enable with programmable polarity (FIFOPINPOLAR.4), selected by IFCONFIG[1:0].
85 PA3/WU2 bidirectional Port A bit 3 I/O or alternate USB wakeup source enabled by WU2EN (WAKEUP.1) with polarity set by WU2POL (WAKEUP.4).
86 D5 bidirectional 8051 data bus bit 5 for external program and data memory, high impedance when inactive and driven LOW in suspend.
87 D6 bidirectional 8051 data bus bit 6 for external program and data memory, high impedance when inactive and driven LOW in suspend.
88 D7 bidirectional 8051 data bus bit 7 for external program and data memory, high impedance when inactive and driven LOW in suspend.
89 PA4/FIFOADR0 bidirectional Port A bit 4 I/O or input-only slave FIFO address select 0, selected by IFCONFIG[1..0].
90 PA5/FIFOADR1 bidirectional Port A bit 5 I/O or input-only slave FIFO address select 1, selected by IFCONFIG[1..0].
91 PA6/PKTEND bidirectional Port A bit 6 I/O or PKTEND input that commits FIFO packet data to the endpoint, polarity programmable via FIFOPINPOLAR.5.
92 PA7/FLAGD/SLCS# bidirectional Port A bit 7 I/O, programmable slave-FIFO output status flag FLAGD, or SLCS# gating all other slave FIFO enable/strobes.
93 GND power_in Ground.
94 A0 output 8051 address bus bit 0, driven at all times and reflecting the internal address when addressing internal RAM.
95 A1 output 8051 address bus bit 1, driven at all times and reflecting the internal address when addressing internal RAM.
96 A2 output 8051 address bus bit 2, driven at all times and reflecting the internal address when addressing internal RAM.
97 A3 output 8051 address bus bit 3, driven at all times and reflecting the internal address when addressing internal RAM.
98 CTL5 output CTL5 is a GPIF control output.
99 RESET# input Active LOW reset that resets the entire chip.
100 VCC power_in VCC, connect to the 3.3-V power source.
101 WAKEUP input USB wakeup with programmable polarity (WAKEUP.4); asserting it starts the oscillator and wakes the 8051 from suspend, and holding it asserted inhibits suspend.
102 PD0/FD8 bidirectional Port D bit 0 I/O or FIFO/GPIF data bus bit 8, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
103 PD1/FD9 bidirectional Port D bit 1 I/O or FIFO/GPIF data bus bit 9, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
104 PD2/FD10 bidirectional Port D bit 2 I/O or FIFO/GPIF data bus bit 10, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
105 PD3/FD11 bidirectional Port D bit 3 I/O or FIFO/GPIF data bus bit 11, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
106 INT5# input 8051 INT5 interrupt request input, edge-sensitive, active LOW.
107 VCC power_in VCC, connect to the 3.3-V power source.
108 PE0/T0OUT bidirectional Port E bit 0 I/O or active-HIGH Timer0 overflow output, selected by PORTECFG.0.
109 PE1/T1OUT bidirectional Port E bit 1 I/O or active-HIGH Timer1 overflow output, selected by PORTECFG.1.
110 PE2/T2OUT bidirectional Port E bit 2 I/O or active-HIGH Timer2 overflow output, selected by PORTECFG.2.
111 PE3/RXD0OUT bidirectional Port E bit 3 I/O or active-HIGH UART0 RXD0OUT output, selected by PORTECFG.3.
112 PE4/RXD1OUT bidirectional Port E bit 4 I/O or active-HIGH UART1 RXD1OUT output, selected by PORTECFG.4.
113 PE5/INT6 bidirectional Port E bit 5 I/O or edge-sensitive active-HIGH 8051 INT6 interrupt input, selected by PORTECFG.5.
114 PE6/T2EX bidirectional Port E bit 6 I/O or Timer2 T2EX input that reloads Timer2 on its falling edge, selected by PORTECFG.6.
115 PE7/GPIFADR8 bidirectional Port E bit 7 I/O or GPIF address output 8, selected by PORTECFG.7.
116 GND power_in Ground.
117 A4 output 8051 address bus bit 4, driven at all times and reflecting the internal address when addressing internal RAM.
118 A5 output 8051 address bus bit 5, driven at all times and reflecting the internal address when addressing internal RAM.
119 A6 output 8051 address bus bit 6, driven at all times and reflecting the internal address when addressing internal RAM.
120 A7 output 8051 address bus bit 7, driven at all times and reflecting the internal address when addressing internal RAM.
121 PD4/FD12 bidirectional Port D bit 4 I/O or FIFO/GPIF data bus bit 12, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
122 PD5/FD13 bidirectional Port D bit 5 I/O or FIFO/GPIF data bus bit 13, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
123 PD6/FD14 bidirectional Port D bit 6 I/O or FIFO/GPIF data bus bit 14, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
124 PD7/FD15 bidirectional Port D bit 7 I/O or FIFO/GPIF data bus bit 15, selected by IFCONFIG[1..0] and EPxFIFOCFG.0.
125 GND power_in Ground.
126 A8 output 8051 address bus bit 8, driven at all times and reflecting the internal address when addressing internal RAM.
127 A9 output 8051 address bus bit 9, driven at all times and reflecting the internal address when addressing internal RAM.
128 A10 output 8051 address bus bit 10, driven at all times and reflecting the internal address when addressing internal RAM.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFP-128(14x20)
Category Embedded Processors & Controllers
Pins 128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.3 3.6 V 43
VCC Ramp Up VCC Ramp Up 200 µs 0 to 3.3 V 43
Input HIGH voltage VIH 2 5.25 V 43
Input LOW voltage VIL -0.5 0.8 V 43
Crystal input HIGH voltage VIH_X 2 5.25 V 43
Crystal input LOW voltage VIL_X -0.5 0.8 V 43
Input leakage current II -10 10 µA 0< VIN < VCC 43
Output voltage HIGH VOH 2.4 V IOUT = 4 mA 43
Output LOW voltage VOL 0.4 V IOUT = -4 mA 43
Output current HIGH IOH 4 mA 43
Output current LOW IOL 4 mA 43
Input pin capacitance (except D+/D-) CIN 10 pF Except D+/D- 43
Input pin capacitance (D+/D-) CIN 15 pF D+/D- 43
Suspend current, connected ISUSP 0.5 1.2 mA CY7C68013/CY7C68015, Connected; measured at Max VCC, 25 °C 43
Suspend current, disconnected ISUSP 0.3 1 mA CY7C68013/CY7C68015, Disconnected; measured at Max VCC, 25 °C 43
Supply current, USB HS ICC 50 85 mA 8051 running, connected to USB HS 43
Supply current, USB FS ICC 35 65 mA 8051 running, connected to USB FS 43
Reset time after valid power TRESET 5 ms VCC min = 3.0 V 43
Pin reset after powered on TRESET 200 µs 43
Storage temperature -65 150 °C 42
Ambient temperature with power supplied (Commercial) 0 70 °C 42
Supply voltage to ground potential -0.5 4 V 42
DC input voltage to any input pin 5.25 V 42
DC voltage applied to outputs in high Z state -0.5 V max VCC + 0.5 V 42
Power dissipation 300 mW 42
Static discharge voltage 2000 V >2000 V 42
Max output current, per I/O port 10 mA 42
Max output current, all five I/O ports 50 mA 128-pin and 100-pin packages 42
Ambient temperature under bias (Commercial) TA 0 70 °C Commercial 42
Supply voltage 3 3.6 V 42
Oscillator or crystal frequency FOSC 24 MHz 24 MHz ± 100 ppm, parallel resonant 42
Maximum junction temperature 125 °C 42
Junction to case thermal resistance θJc 15.5 °C/W 128 TQFP, ambient 70 °C 42
Junction to ambient thermal resistance θJa 43.2 °C/W 128 TQFP, ambient 70 °C 42
Delay from clock to valid address (program read) tAV 0 10.7 ns 44
Clock to PSEN LOW tSTBL 0 8 ns 44
Clock to PSEN HIGH tSTBH 0 8 ns 44
Clock to OE LOW (program read) tSOEL 11.1 ns 44
Clock to CS LOW (program read) tSCSL 13 ns 44
Data setup to clock (program read) tDSU 9.6 ns 44
Data hold time (program read) tDH 0 ns 44
Delay from clock to valid address (data read) tAV 10.7 ns 45
Clock to RD LOW tSTBL 11 ns 45
Clock to RD HIGH tSTBH 11 ns 45
Clock to CS LOW (data read) tSCSL 13 ns 45
Clock to OE LOW (data read) tSOEL 11.1 ns 45
Data setup to clock (data read) tDSU 9.6 ns 45
Data hold time (data read) tDH 0 ns 45

CAD (KiCad official)

  • Symbol: CY7C68013A-128AXC
  • Footprint: Package_QFP:LQFP-128_14x20mm_P0.5mm
  • 3D model: QFP-128(14x20) (KiCad packages3D, STEP)
  • 3D model files: cy7c68013a-128axc-etched.step / cy7c68013a-128axc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c68013a-128axc.step / cy7c68013a-128axc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (75 pp, sha256 67d39521d4c85939, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF