CY7C65642-28LTXCT

{
  "schema_version": 1,
  "type": "component",
  "slug": "cy7c65642-28ltxct",
  "title": "CY7C65642-28LTXCT",
  "brief": "Infineon Cypress Semicon USB Converters, QFN-28(5x5). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface",
    "cy7c65642-28ltxct"
  ],
  "component": {
    "mpn": "CY7C65642-28LTXCT",
    "manufacturer": "Infineon Cypress Semicon",
    "package": "QFN-28(5x5)",
    "pin_count": 29,
    "category": "Interface",
    "subcategory": "USB Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590221303329558528",
    "parts": {
      "symbol": "cy7c65642-28ltxct.kicad_sym",
      "footprint": "cy7c65642-28ltxct.kicad_mod",
      "model_3d": "cy7c65642-28ltxct-etched.glb",
      "model_3d_plain": "cy7c65642-28ltxct.glb",
      "model_3d_step": "cy7c65642-28ltxct-etched.step",
      "model_3d_step_plain": "cy7c65642-28ltxct.step",
      "lbr": "cy7c65642-28ltxct.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "D-",
        "type": "bidirectional",
        "description": "Upstream USB 2.0 D- signal (high/full-speed)."
      },
      {
        "number": "2",
        "name": "D+",
        "type": "bidirectional",
        "description": "Upstream USB 2.0 D+ signal (high/full-speed). Internal 1.5 k pull-up integrated."
      },
      {
        "number": "3",
        "name": "DD-[1]",
        "type": "bidirectional",
        "description": "Downstream Port 1 USB 2.0 D- signal. Integrated pull-down and series termination."
      },
      {
        "number": "4",
        "name": "DD+[1]",
        "type": "bidirectional",
        "description": "Downstream Port 1 USB 2.0 D+ signal. Integrated pull-down and series termination."
      },
      {
        "number": "5",
        "name": "VCC_A",
        "type": "power_in",
        "description": "3.3 V analog power supply to the chip."
      },
      {
        "number": "6",
        "name": "DD-[2]",
        "type": "bidirectional",
        "description": "Downstream Port 2 USB 2.0 D- signal. Integrated pull-down and series termination."
      },
      {
        "number": "7",
        "name": "DD+[2]",
        "type": "bidirectional",
        "description": "Downstream Port 2 USB 2.0 D+ signal. Integrated pull-down and series termination."
      },
      {
        "number": "8",
        "name": "RREF",
        "type": "passive",
        "description": "Bias reference. Connect a 649 ohm precision resistor between RREF and GND."
      },
      {
        "number": "9",
        "name": "VCC_A",
        "type": "power_in",
        "description": "3.3 V analog power supply to the chip."
      },
      {
        "number": "10",
        "name": "XIN",
        "type": "input",
        "description": "12-MHz crystal clock input, or 12-MHz external clock input."
      },
      {
        "number": "11",
        "name": "XOUT",
        "type": "output",
        "description": "12-MHz crystal driver output. Leave NC if an external clock is driving XIN."
      },
      {
        "number": "12",
        "name": "DD-[3]",
        "type": "bidirectional",
        "description": "Downstream Port 3 USB 2.0 D- signal. Integrated pull-down and series termination."
      },
      {
        "number": "13",
        "name": "DD+[3]",
        "type": "bidirectional",
        "description": "Downstream Port 3 USB 2.0 D+ signal. Integrated pull-down and series termination."
      },
      {
        "number": "14",
        "name": "VCC_A",
        "type": "power_in",
        "description": "3.3 V analog power supply to the chip."
      },
      {
        "number": "15",
        "name": "DD-[4]",
        "type": "bidirectional",
        "description": "Downstream Port 4 USB 2.0 D- signal. Integrated pull-down and series termination."
      },
      {
        "number": "16",
        "name": "DD+[4]",
        "type": "bidirectional",
        "description": "Downstream Port 4 USB 2.0 D+ signal. Integrated pull-down and series termination."
      },
      {
        "number": "17",
        "name": "RESET#",
        "type": "input",
        "description": "Active-LOW external reset input; internal 10 k pull-up. Driving low forces the entire chip to the initial state."
      },
      {
        "number": "18",
        "name": "TEST/I2C_SCL",
        "type": "bidirectional",
        "description": "Multiplexed test/I2C clock pin (internal pull-down). Acts as I2C_SCL when an EEPROM is used; logic-high at boot puts the chip in test mode."
      },
      {
        "number": "19",
        "name": "OVR#[4]",
        "type": "input",
        "description": "Active-LOW overcurrent detection input for Downstream Port 4. Internal pull-up. Disabled in Gang mode."
      },
      {
        "number": "20",
        "name": "OVR#[3]",
        "type": "input",
        "description": "Active-LOW overcurrent detection input for Downstream Port 3. Internal pull-up. Disabled in Gang mode."
      },
      {
        "number": "21",
        "name": "VCC_D",
        "type": "power_in",
        "description": "3.3 V digital power supply to the chip."
      },
      {
        "number": "22",
        "name": "SELFPWR",
        "type": "input",
        "description": "Self/bus power select input. 0 = bus-powered, 1 = self-powered."
      },
      {
        "number": "23",
        "name": "GANG",
        "type": "bidirectional",
        "description": "Gang/individual power switching mode select and status. Defaults to input after POR: input=1 selects Gang mode (output=0 normal, 1 suspend); input=0 selects Individual mode (output=1 normal, 0 suspend)."
      },
      {
        "number": "24",
        "name": "OVR#[2]",
        "type": "input",
        "description": "Active-LOW overcurrent detection input for Downstream Port 2. Internal pull-up. Disabled in Gang mode."
      },
      {
        "number": "25",
        "name": "OVR#[1]",
        "type": "input",
        "description": "Active-LOW overcurrent detection input for Downstream Port 1. Internal pull-up. Only OVR#[1] is enabled in Gang mode (represents ganged overcurrent)."
      },
      {
        "number": "26",
        "name": "PWR#/I2C_SDA",
        "type": "bidirectional",
        "description": "Multiplexed power-switch driver output (active-LOW, default) and I2C data pin. Acts as I2C_SDA when an EEPROM is present; otherwise drives an external port power switch."
      },
      {
        "number": "27",
        "name": "VCC",
        "type": "power_in",
        "description": "5 V input to the internal LDO regulator. Leave NC when powering the chip from an external 3.3 V regulator."
      },
      {
        "number": "28",
        "name": "VREG",
        "type": "power_out",
        "description": "Internal 5 V-to-3.3 V regulator output (when using internal regulation); also serves as 3.3 V input when using an external regulator."
      },
      {
        "number": "PAD",
        "name": "GND",
        "type": "power_in",
        "description": "Solderable exposed thermal pad on the underside of the QFN. Sole ground return for the chip; must be soldered to the PCB ground plane."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590221303329558528",
        "pages": 40,
        "sha256": "e73715d79d8d5fce",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 29,
        "described": 29,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "cy7c65642-28ltxct.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          5,
          5,
          0.92
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "e9d6d740f505b03e5aa0ac826330f9e269344b84656d051f50eb07ac162749eb",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cy7c65642-28ltxct-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          5,
          5,
          0.92
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "5d4fe711c0fc2768e0310cd0b61bb1bc00a52823936249ed3cd5b5727bf0e0dd",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Infineon Cypress Semicon",
      "Package": "QFN-28(5x5)",
      "Category": "Interface",
      "Pins": "29"
    }
  },
  "variants": [
    {
      "mpn": "CY7C65642-28LTXCT",
      "kind": "packaging"
    },
    {
      "mpn": "CY7C65642-28LTXCT48AXC",
      "kind": "packaging"
    },
    {
      "mpn": "CY7C65642-28LTXCT48AXCT",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
    "cy7c65642-28ltxct"
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  "discovery_pitch": "CY7C65642-28LTXCT (Infineon Cypress Semicon) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cy7c65642-28ltxct.kicad_sym",
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    "cy7c65642-28ltxct.step",
    "cy7c65642-28ltxct.lbr",
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    "docs/cy7c65642-28ltxct-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
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  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T19:36:38.255Z"
}