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CY7C64215-56LTXC

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy7c64215-56ltxcfactory-2.0.0extractor-text

Verified CY7C64215-56LTXC

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 57 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY7C64215-56LTXC · QFN-56-EP(8x8) · 57 pins
  • ✓copper: 57 copper pads, none touching another net
  • ✓datasheet: all 57 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C2953847, digikey CY7C64215-56LTXC-ND, mouser 727-CY7C64215-56LTXC
  • ✓family: QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-19_zczjo/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 57 pins = 57 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 57 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy7c64215-56ltxc.kicad_sym✓ cy7c64215-56ltxc.kicad_mod✓ cy7c64215-56ltxc.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

CY7C64215-56LTXC

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-56-EP(8x8)

CY7C64215-56LTXC from Cypress Semicon, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[3] bidirectional Port 2 bit 3 GPIO, direct switched capacitor block input, analog mux input.
2 P2[1] bidirectional Port 2 bit 1 GPIO, direct switched capacitor block input, analog mux input.
3 P4[7] bidirectional Port 4 bit 7 GPIO with analog mux input.
4 P4[5] bidirectional Port 4 bit 5 GPIO with analog mux input.
5 P4[3] bidirectional Port 4 bit 3 GPIO with analog mux input.
6 P4[1] bidirectional Port 4 bit 1 GPIO with analog mux input.
7 P3[7] bidirectional Port 3 bit 7 GPIO with analog mux input.
8 P3[5] bidirectional Port 3 bit 5 GPIO with analog mux input.
9 P3[3] bidirectional Port 3 bit 3 GPIO with analog mux input.
10 P3[1] bidirectional Port 3 bit 1 GPIO with analog mux input.
11 P5[7] bidirectional Port 5 bit 7 GPIO with analog mux input.
12 P5[5] bidirectional Port 5 bit 5 GPIO with analog mux input.
13 P5[3] bidirectional Port 5 bit 3 GPIO with analog mux input.
14 P5[1] bidirectional Port 5 bit 1 GPIO with analog mux input.
15 P1[7] bidirectional Port 1 bit 7 GPIO with analog mux input, also I2C serial clock (SCL).
16 P1[5] bidirectional Port 1 bit 5 GPIO with analog mux input, also I2C serial data (SDA).
17 P1[3] bidirectional Port 1 bit 3 GPIO with analog mux input.
18 P1[1] bidirectional Port 1 bit 1 GPIO with analog mux input, also I2C SCL and ISSP-SCLK.
19 VSS power_in Ground connection.
20 D+ bidirectional USB full-speed (12 Mbps) data line D+.
21 D- bidirectional USB full-speed (12 Mbps) data line D-.
22 VDD power_in Supply voltage; operates at 3.15 V to 3.5 V or 4.35 V to 5.25 V per the datasheet features.
23 P7[7] bidirectional Port 7 bit 7 GPIO.
24 P7[0] bidirectional Port 7 bit 0 GPIO.
25 P1[0] bidirectional Port 1 bit 0 GPIO with analog mux input, also I2C SDA and ISSP-SDATA.
26 P1[2] bidirectional Port 1 bit 2 GPIO with analog mux input.
27 P1[4] bidirectional Port 1 bit 4 GPIO with analog mux input, also optional external clock input EXTCLK.
28 P1[6] bidirectional Port 1 bit 6 GPIO with analog mux input.
29 P5[0] bidirectional Port 5 bit 0 GPIO with analog mux input.
30 P5[2] bidirectional Port 5 bit 2 GPIO with analog mux input.
31 P5[4] bidirectional Port 5 bit 4 GPIO with analog mux input.
32 P5[6] bidirectional Port 5 bit 6 GPIO with analog mux input.
33 P3[0] bidirectional Port 3 bit 0 GPIO with analog mux input.
34 P3[2] bidirectional Port 3 bit 2 GPIO with analog mux input.
35 P3[4] bidirectional Port 3 bit 4 GPIO with analog mux input.
36 P3[6] bidirectional Port 3 bit 6 GPIO with analog mux input.
37 P4[0] bidirectional Port 4 bit 0 GPIO with analog mux input.
38 P4[2] bidirectional Port 4 bit 2 GPIO with analog mux input.
39 P4[4] bidirectional Port 4 bit 4 GPIO with analog mux input.
40 P4[6] bidirectional Port 4 bit 6 GPIO with analog mux input.
41 P2[0] bidirectional Port 2 bit 0 GPIO, direct switched capacitor block input, analog mux input.
42 P2[2] bidirectional Port 2 bit 2 GPIO, direct switched capacitor block input, analog mux input.
43 P2[4] bidirectional Port 2 bit 4 GPIO, serves as external analog ground (AGND) input.
44 P2[6] bidirectional Port 2 bit 6 GPIO, serves as external voltage reference (VREF) input.
45 P0[0] bidirectional Port 0 bit 0 GPIO, analog column mux input.
46 P0[2] bidirectional Port 0 bit 2 GPIO, analog column mux input and column output.
47 P0[4] bidirectional Port 0 bit 4 GPIO, analog column mux input and column output.
48 P0[6] bidirectional Port 0 bit 6 GPIO, analog column mux input.
49 VDD power_in Supply voltage; operates at 3.15 V to 3.5 V or 4.35 V to 5.25 V per the datasheet features.
50 VSS power_in Ground connection.
51 P0[7] bidirectional Port 0 bit 7 GPIO, analog column mux input.
52 P0[5] bidirectional Port 0 bit 5 GPIO, analog column mux input and column output.
53 P0[3] bidirectional Port 0 bit 3 GPIO, analog column mux input and column output.
54 P0[1] bidirectional Port 0 bit 1 GPIO, analog column mux input.
55 P2[7] bidirectional Port 2 bit 7 GPIO with analog mux input.
56 P2[5] bidirectional Port 2 bit 5 GPIO with analog mux input.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-56-EP(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 100 °C 14
Supply voltage on VDD relative to VSS VDD -0.5 6 V 14
Maximum current into any port pin IMIO -25 50 mA 14
Maximum current into any port pin configured as an analog driver IMAIO -50 50 mA 14
Electrostatic discharge voltage ESD 2000 V Human body model ESD. 14
Latch up current LU 200 mA 14
Commercial ambient temperature TAC 0 70 °C 14
Industrial ambient temperature TAI -40 85 °C USB operation requires external clock oscillator and 56-pin QFN package. 14
Junction temperature TJ -40 100 °C 14
Supply voltage VDD 3 5.25 V 15
Supply current, IMO = 24 MHz (5 V) IDD5 14 27 mA Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. 15
Supply current, IMO = 24 MHz (3.3 V) IDD3 8 14 mA Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. 15
Sleep (mode) current with POR, LVD, sleep timer, and WDT ISB 3 6.5 µA Conditions are with internal slow speed oscillator, VDD = 3.3 V, 0 °C < TA < 55 °C, analog power = off. 15
Sleep (mode) current at high temperature ISBH 4 25 µA Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA < 70 °C, analog power = off. 15
Pull-up resistor RPU 4 5.6 8 kΩ 16
Pull-down resistor RPD 4 5.6 8 kΩ 16
Low output level VOL 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V 16
High-level source current IOH 10 mA 16
Low-level sink current IOL 25 mA 16
Input low level VIL 0.8 V VDD = 3.15 to 5.25. 16
Input high level VIH 2.1 V VDD = 3.15 to 5.25. 16
Capacitive load on pins as input CIN 3.5 10 pF Package and pin dependent. Temp = 25 °C. 16
Capacitive load on pins as output COUT 3.5 10 pF Package and pin dependent. Temp = 25 °C. 16
Differential input sensitivity VDI 0.2 V / (D+), (D-) / 16
Differential input common mode range VCM 0.8 2.5 V 16
Single-ended receiver threshold VSE 0.8 2 V 16
Transceiver capacitance CIN 20 pF 16
High Z state data line leakage IIO -10 10 µA 0 V < VIN < 3.3 V. 16
External USB series resistor REXT 23 25 Ω In series with each USB pin. 16
Static output high, driven VUOH 2.8 3.6 V 15 kΩ ± 5% to ground. Internal pull-up enabled. 16
Static output high, idle VUOHI 2.7 3.6 V 15 kΩ ± 5% to ground. Internal pull-up enabled. 16
Static output low VUOL 0.3 V 15 kΩ ± 5% to ground. Internal pull-up enabled. 16
USB driver output impedance ZO 28 44 Ω Including REXT resistor. 16
D+/D- crossover voltage VCRS 1.3 2 V 16
VDD for programming and erase VDDP 4.5 5 5.5 V 24
Supply voltage for flash write operation VDDIWRITE 3.15 5.25 V 24
Supply current during programming or verify IDDP 15 30 mA 24
Input low voltage during programming or verify VILP 0.8 V 24
Input high voltage during programming or verify VIHP 2.1 V 24
Input current when applying VILP to P1[0] or P1[1] IILP 0.2 mA Driving internal pull-down resistor. 24
Input current when applying VIHP to P1[0] or P1[1] IIHP 1.5 mA Driving internal pull-down resistor. 24
Flash endurance (per block) FlashENPB 50000 Erase/write cycles per block. 24
Flash endurance (total) FlashENT 1.8e+06 Erase/write cycles. 24
Flash data retention FlashDR 10 Years 24
IMO frequency for 24 MHz (5 V) FIMO245V 23.04 24 24.96 MHz Trimmed for 5 V operation using factory trim values. 25
IMO frequency for 24 MHz (3.3 V) FIMO243V 22.08 24 25.92 MHz Trimmed for 3.3 V operation using factory trim values. 25
IMO frequency with USB frequency locking enabled and USB traffic present FIMOUSB 23.94 24 24.06 MHz USB operation for system clock source from the IMO is limited to 0°C < TA < 70°C. 25
CPU frequency (5 V nominal) FCPU1 0.09 24 24.96 MHz SLIMO mode = 0. 25
CPU frequency (3.3 V nominal) FCPU2 0.086 12 12.96 MHz SLIMO mode = 0. 25
Digital PSoC block frequency (5 V nominal) FBLK5 0 48 49.92 MHz 25
ILO frequency F32K1 15 32 64 kHz 25
ILO untrimmed frequency F32K_U 5 100 kHz After a reset and before the M8C starts to run, the ILO is not trimmed. 25
ILO duty cycle DCILO 20 50 80 % 25
24-MHz duty cycle DC24M 40 50 60 % 25
48-MHz output frequency Fout48M 46.08 48 49.92 MHz Trimmed. Using factory trim values. 25
Maximum frequency of signal on row input or row output FMAX 12.96 MHz 25
Power supply slew rate SRPOWER_UP 250 V/ms 25
Time from end of POR to CPU executing code TPOWERUP 16 100 ms 25
GPIO operating frequency FGPIO 0 12 MHz Normal Strong Mode 26
Typical junction-to-ambient thermal impedance, 56-pin QFN JA 20 °C/W 56-pin QFN 33

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 7

CAD (KiCad official)

  • Symbol: CY7C64215-56LTXC
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy7c64215-56ltxc-etched.step / cy7c64215-56ltxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c64215-56ltxc.step / cy7c64215-56ltxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (46 pp, sha256 0b74c71e9480da7a, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF