CY7C63823-SXC from Cypress Semicon, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	No connect.
2	P0.7	bidirectional	GPIO Port 0 bit 7, configured individually.
3	P0.6/TIO1	bidirectional	GPIO Port 0 bit 6, configured individually; alternate function is timer capture input or timer output TIO1.
4	P0.5/TIO0	bidirectional	GPIO Port 0 bit 5, configured individually; alternate function is timer capture input or timer output TIO0.
5	P0.4/INT2	bidirectional	GPIO Port 0 bit 4, configured individually; optional rising edge interrupt INT2.
6	P0.3/INT1	bidirectional	GPIO Port 0 bit 3, configured individually; optional rising edge interrupt INT1.
7	P0.2/INT0	bidirectional	GPIO Port 0 bit 2, configured individually; optional rising edge interrupt INT0.
8	P0.1	bidirectional	GPIO Port 0 bit 1, configured individually; clock output when configured as Clock Out.
9	P0.0	bidirectional	GPIO Port 0 bit 0, configured individually; external clock input when configured as Clock In.
10	P2.1	bidirectional	GPIO Port 2, configured as a group (byte).
11	P2.0	bidirectional	GPIO Port 2, configured as a group (byte).
12	VSS	power_in	Ground.
13	P1.0/D+	bidirectional	GPIO Port 1 bit 0 / USB D+ / ISSP-SCLK; draws current if used as a general purpose output, so configure as an input to reduce current draw.
14	P1.1/D-	bidirectional	GPIO Port 1 bit 1 / USB D- / ISSP-SDATA; draws current if used as a general purpose output, so configure as an input to reduce current draw.
15	VCC	power_in	Supply voltage (operating range 4.0 V to 5.5 V).
16	P1.2/VREG	bidirectional	GPIO Port 1 bit 2, configured individually; 3.3 V regulator output when enabled, requiring a 1 µF min, 2 µF max capacitor on the Vreg output.
17	P1.3/SSEL	bidirectional	GPIO Port 1 bit 3, configured individually; alternate function is SSEL signal of the SPI bus with TTL voltage thresholds.
18	P3.0	bidirectional	GPIO Port 3, configured as a group (byte).
19	P3.1	bidirectional	GPIO Port 3, configured as a group (byte).
20	P1.4/SCLK	bidirectional	GPIO Port 1 bit 4, configured individually; alternate function is SCLK signal of the SPI bus with TTL voltage thresholds.
21	P1.5/SMOSI	bidirectional	GPIO Port 1 bit 5, configured individually; alternate function is SMOSI signal of the SPI bus with TTL voltage thresholds.
22	P1.6/SMISO	bidirectional	GPIO Port 1 bit 6, configured individually; alternate function is SMISO signal of the SPI bus with TTL voltage thresholds.
23	P1.7	bidirectional	GPIO Port 1 bit 7, configured individually, with TTL voltage threshold.
24	NC	unconnected	No connect.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	SOIC-24-300mil
Category	Embedded Processors & Controllers
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature		-40		90	°C		73
Ambient temperature with power applied		0		70	°C		73
Supply voltage on VCC relative to VSS	VCC	-0.5		7	V		73
DC input voltage (max is VCC + 0.5 V)		-0.5			V	upper limit printed as + VCC + 0.5 V	73
DC voltage applied to outputs in High-Z state (max is VCC + 0.5 V)		-0.5			V	upper limit printed as + VCC + 0.5 V	73
Maximum total sink current into Port 0 and Port 1 pins				70	mA		73
Maximum total source output current into GPIO pins				30	mA		73
Maximum on-chip power dissipation on any GPIO pin				50	mW		73
Power dissipation				300	mW		73
Static discharge voltage				2200	V		73
Latch up current				200	mA		73
Operating voltage	VCC1	4		5.5	V	No USB activity, CPU speed < 12 MHz	73
Operating voltage	VCC2	4.35		5.25	V	USB activity, CPU speed < 12 MHz	73
Operating voltage	VCC4	4.75		5.5	V	No USB activity, CPU speed is between 12 MHz and 24 MHz	73
Operating temp	TFP	0		70	°C	Flash programming	73
VCC operating supply current	ICC1			40	mA	VCC = 5.25 V, no GPIO loading, 24 MHz	73
VCC operating supply current	ICC2		10		mA	VCC = 5.0 V, no GPIO loading, 6 MHz	73
Standby current	ISB1			10	µA	Internal and external oscillators, bandgap, flash, CPU clock, timer clock, USB clock all disabled	73
Low-voltage detect trip voltage (8 programmable trip points)	VLVD	2.681		4.872	V		73
Max regulator output current	IVREG			125	mA	4.35 V < VCC < 5.5 V	73
Keep alive current	IKA			20	µA	When regulator is disabled with "keep alive" enable	73
Keep alive voltage	VKA	2.35		3.8	V	Keep alive bit set in VREGCR	73
VREG output voltage	VREG1	3		3.6	V	VCC > 4.35 V, 0 < temp < 40 °C, 25 mA < IVREG < 125 mA (3.3V ± 8%), T = 0 to 70 °C	73
VREG output voltage	VREG2	3.15		3.45	V	VCC > 4.35 V, 0 < temp < 40 °C, 1 mA < IVREG < 25 mA (3.3V ± 4%), T = 0 to 40 °C	73
Capacitive load on Vreg pin	CLOAD	1		2	µF		73
Line regulation	LNREG			1	%/V		73
Load regulation	LDREG			0.04	%/mA		73
Static output high	VON	2.8		3.6	V	15 K ± 5% Ohm to VSS	73
Static output low	VOFF			0.3	V	RUP is enabled	73
Differential input sensitivity	VDI	0.2			V		74
Differential input common mode range	VCM	0.8		2.5	V		74
Single ended receiver threshold	VSE	0.8		2	V		74
Transceiver capacitance	CIN			20	pF		74
Hi-Z state data line leakage	IIO	-10		10	µA	0V < VIN < 3.3 V	74
PS/2 static output low	VOLP			0.4	V	SDATA or SCLK pins	74
Internal PS/2 pull-up resistance	RPS2	3		7	kΩ	SDATA, SCLK pins, PS/2 Enabled	74
GPIO pull-up resistance	RUP	4		12	kΩ		74
Input threshold voltage low, CMOS mode	VICR	40		65	% VCC	Low to High edge	74
Input threshold voltage low, CMOS mode	VICF	30		55	% VCC	High to Low edge	74
Input hysteresis voltage, CMOS mode	VHC	3		10	% VCC	High to low edge	74
Input low voltage, TTL mode	VILTTL			0.8	V	I/O pin Supply = 4.0-5.5 V	74
Input high voltage, TTL mode	VIHTTL	2			V	I/O pin Supply = 4.0-5.5 V	74
Output low voltage, high drive	VOL1			0.8	V	IOL1 = 50 mA	74
Output low voltage, high drive	VOL2			0.4	V	IOL1 = 25 mA	74
Output low voltage, low drive	VOL3			0.4	V	IOL2 = 8 mA	74
Maximum load capacitance	CLOAD			50	pF		74
External clock duty cycle	TECLKDC	45		55	%		75
External clock frequency	TECLK1	0.187		24	MHz	External clock is the source of the CPUCLK	75
External clock frequency	TECLK2	0		24	MHz	External clock is not the source of the CPUCLK	75
Internal main oscillator frequency	FIMO1	22.8		25.2	MHz	No USB present	75
Internal main oscillator frequency	FIMO2	23.64		24.3	MHz	With USB present	75
Internal low power oscillator	FILO1	29.44		37.12	kHz	Normal mode	75
Internal low power oscillator	FILO2	35.84		47.36	kHz	Low power mode	75
Output ripple voltage	VORIP			200	mVp-p	10 Hz to 100 MHz at CLOAD = 1 µF	75
Transition rise time	TR1	75			ns	CLOAD = 200 pF	75
Transition rise time	TR2			300	ns	CLOAD = 600 pF	75
Transition fall time	TF2			300	ns	CLOAD = 600 pF	75
Rise/fall time matching	TR	80		125	%		75
Output signal crossover voltage	VCRS	1.3		2	V		75

CAD (KiCad official)

Symbol: CY7C63823-SXC
Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
3D model: SOIC-24-300mil (KiCad packages3D, STEP)
3D model files: cy7c63823-sxc-etched.step / cy7c63823-sxc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c63823-sxc.step / cy7c63823-sxc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (91 pp, sha256 e2cac081aa9d4475, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY7C63823-SXC

Verified CY7C63823-SXC

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README