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CY7C53120E4-40SXIT

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Cypress Semicon Pre-ordered Products, SOIC-32. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY7C53120E4-40SXIT

Cypress Semicon · Pre-ordered Products · SOIC-32

CY7C53120E4-40SXIT from Cypress Semicon, in a SOIC-32. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET bidirectional Active-low reset pin with built-in pull-up; allowable external capacitance is 100-1000 pF.
2 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.
3 I/O4 bidirectional General I/O port pin with built-in configurable pull-up; may drive the input to Timer/Counter 1 or Timer/Counter 2.
4 I/O3 bidirectional General I/O port pin with large current-sink capacity (20 mA).
5 I/O2 bidirectional General I/O port pin with large current-sink capacity (20 mA).
6 I/O1 bidirectional General I/O port pin with 20 mA sink capacity; Timer/Counter 2 output may be routed here.
7 I/O0 bidirectional General I/O port pin with 20 mA sink capacity; Timer/Counter 1 output may be routed here.
8 SERVICE bidirectional Active-low service pin with built-in configurable pull-up; alternates between input and output at a 76-Hz rate.
9 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
10 Vpp input In-circuit test mode control; if high when RESET is asserted, the I/O, address and data buses become Hi-Z.
11 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.
12 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.
13 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
14 CLK2 output Oscillator connection; leave open when an external clock is input to CLK1, maximum of one external load.
15 CLK1 input Oscillator connection or external clock input.
16 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
17 CP2 bidirectional Communication port pin supporting single-ended, special purpose and differential modes (bit clock output in special purpose mode, transceiver enable in single-ended mode, differential driver in differential mode).
18 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.
19 CP0 bidirectional Communication port pin used for receiving serial data; forms the differential receiver with CP1 in differential mode.
20 CP1 bidirectional Communication port pin used for transmitting serial data; forms the differential receiver with CP0 in differential mode.
21 CP3 bidirectional Communication port pin that forms the differential driver with CP2 in differential mode.
22 CP4 bidirectional Communication port pin that transmits a frame clock in special purpose mode.
23 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
24 I/O10 bidirectional General I/O port pin; may be used for serial communication under firmware control.
25 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.
26 I/O9 bidirectional General I/O port pin; may be used for serial communication under firmware control.
27 I/O8 bidirectional General I/O port pin; may be used for serial communication under firmware control.
28 I/O7 bidirectional General I/O port pin with built-in configurable pull-up; may drive the input to Timer/Counter 1.
29 I/O6 bidirectional General I/O port pin with built-in configurable pull-up; may drive the input to Timer/Counter 1.
30 I/O5 bidirectional General I/O port pin with built-in configurable pull-up; may drive the input to Timer/Counter 1.
31 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
32 VDD power_in Power input (5 V nom); all VDD pins must be connected together externally.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-32
Category Electronic Tools/Instruments/Consumables
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Low Voltage VIL 0.8 V I/O0-I/O10, CP0, CP3, CP4, SERVICE, D0-D7, RESET; VDD = 4.5 V-5.5 V 9
Input High Voltage VIH 2 V I/O0-I/O10, CP0, CP3, CP4, SERVICE, D0-D7, RESET; VDD = 4.5 V-5.5 V 9
Low-Level Output Voltage VOL 0.1 V Iout < 20 µA 9
Low-Level Output Voltage, standard outputs VOL 0.4 V Standard Outputs (IOL = 1.4 mA) 9
Low-Level Output Voltage, high sink VOL 0.8 V High Sink (I/O0-I/O3), SERVICE, RESET (IOL = 20 mA) 9
Low-Level Output Voltage, high sink VOL 0.4 V High Sink (I/O0-I/O3), SERVICE, RESET (IOL = 10 mA) 9
Low-Level Output Voltage, maximum sink VOL 1 V Maximum Sink (CP2, CP3) (IOL = 40 mA) 9
Low-Level Output Voltage, maximum sink VOL 0.4 V Maximum Sink (CP2, CP3) (IOL = 15 mA) 9
Hysteresis (Excluding CLK1) Vhys 175 mV 9
Input Current (Excluding Pull Ups) Iin -10 10 µA VSS to VDD 9
Pull Up Source Current Ipu 60 260 µA Vout = 0 V, Output = High-Z 9
Operating Mode Supply Current IDD 55 mA 40-MHz Clock 9
Operating Mode Supply Current IDD 32 mA 20-MHz Clock 9
Operating Mode Supply Current IDD 20 mA 10-MHz Clock 9
Operating Mode Supply Current IDD 12 mA 5-MHz Clock 9
Operating Mode Supply Current IDD 8 mA 2.5-MHz Clock 9
Operating Mode Supply Current IDD 7 mA 1.25-MHz Clock 9
Operating Mode Supply Current IDD 3 mA 0.625-MHz Clock 9
Sleep Mode Supply Current IDDsleep 100 µA 9
LVI Trip Point VDD 3.8 4.1 4.4 V CY7C53120E4 9
Receiver Common Mode Voltage Range to maintain hysteresis 1.2 V max is VDD, 2.2 V 10
Receiver Common Mode Range to operate with unspecified hysteresis 0.9 V max is VDD, 1.75 V 10
Propagation Delay 230 ns F = 0, VID = Vhys/2 + 200 mV 10
Input Resistance 5 MΩ 10
Wake-up Time 10 µs 10
Differential Output Impedance for CP2 and CP3 35 Ω Z0 = /V[CP2]-V[CP3]//40 mA for 4.75 < VDD < 5.25 V 10
Thermal resistance junction to ambient, 32-pin SOIC θJA 51 °C/W 32-pin SOIC 1
Maximum Junction Temperature TJunction 105 °C 1

CAD (KiCad official)

  • Symbol: CY7C53120E4-40SXIT
  • Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
  • 3D model: SOIC-32, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cy7c53120e4-40sxit-etched.step / cy7c53120e4-40sxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c53120e4-40sxit.step / cy7c53120e4-40sxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (19 pp, sha256 78effbe30b11228d, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF