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CY7C53120E4-40AXI

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy7c53120e4-40axifactory-2.0.0extractor-text

Verified CY7C53120E4-40AXI

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 44 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY7C53120E4-40AXI · TQFP-44(10x10) · 44 pins
  • ✓copper: 44 copper pads, none touching another net
  • ✓datasheet: all 44 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C2949118, digikey CY7C53120E4-40AXI-ND, mouser 727-CYC53120E440AXI
  • ✓family: TQFP-44_10x10mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-hoj3wjlf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 44 pins = 44 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 44 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy7c53120e4-40axi.kicad_sym✓ cy7c53120e4-40axi.kicad_mod✓ cy7c53120e4-40axi.step
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CY7C53120E4-40AXI

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-44(10x10)

CY7C53120E4-40AXI from Cypress Semicon, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
2 I/O2 bidirectional General I/O port pin with large current-sink capacity (20 mA).
3 I/O1 bidirectional General I/O port pin with 20 mA sink capacity; the output of Timer/Counter 2 may be routed to I/O1.
4 I/O0 bidirectional General I/O port pin with 20 mA sink capacity; the output of Timer/Counter 1 may be routed to I/O0.
5 SERVICE bidirectional Service pin (active LOW) with built-in configurable pull-up that alternates between input and output at a 76-Hz rate.
6 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
7 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
8 Vpp input In-circuit test mode control; if Vpp is high when RESET is asserted, the I/O, address and data buses become Hi-Z.
9 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
10 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
11 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
12 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
13 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
14 CLK2 output Oscillator connection; leave open when an external clock is input to CLK1, maximum of one external load.
15 CLK1 input Oscillator connection or external clock input.
16 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
17 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
18 CP2 bidirectional Communication port pin CP2 of the 5-pin port supporting communications in three modes (enables external transceiver in single-ended mode, differential driver in differential mode).
19 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
20 CP0 bidirectional Communication port pin CP0 of the 5-pin port supporting communications in three modes (serial data receive, differential receiver input).
21 CP1 bidirectional Communication port pin CP1 of the 5-pin port supporting communications in three modes (serial data transmit, differential receiver input).
22 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
23 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
24 CP3 bidirectional Communication port pin CP3 of the 5-pin port supporting communications in three modes (forms the differential driver with CP2).
25 CP4 bidirectional Communication port pin CP4 of the 5-pin port supporting communications in three modes (frame clock in special purpose mode).
26 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
27 I/O10 bidirectional General I/O port pin that may be used for serial communication under firmware control.
28 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
29 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
30 I/O9 bidirectional General I/O port pin that may be used for serial communication under firmware control.
31 I/O8 bidirectional General I/O port pin that may be used for serial communication under firmware control.
32 I/O7 bidirectional General I/O port pin with built-in configurable pull-up; the input to Timer/Counter 1 may be derived from one of I/O4-I/O7.
33 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
34 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
35 I/O6 bidirectional General I/O port pin with built-in configurable pull-up; the input to Timer/Counter 1 may be derived from one of I/O4-I/O7.
36 I/O5 bidirectional General I/O port pin with built-in configurable pull-up; the input to Timer/Counter 1 may be derived from one of I/O4-I/O7.
37 VSS power_in Power input (0 V, GND); all VSS pins must be connected together externally.
38 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
39 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.
40 RESET bidirectional Reset pin (active LOW) with built-in pull-up; allowable external capacitance on RESET is 100-1000 pF.
41 VDD power_in Power input (5 V nominal); all VDD pins must be connected together externally.
42 I/O4 bidirectional General I/O port pin with built-in configurable pull-up; the input to Timer/Counter 1 may be derived from I/O4-I/O7 and the input to Timer/Counter 2 from I/O4.
43 I/O3 bidirectional General I/O port pin with large current-sink capacity (20 mA).
44 NC unconnected No connect; must not be connected on the user's PC board since it may be connected internally to the chip.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-44(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Low Voltage VIL 0.8 V I/O0-I/O10, CP0, CP3, CP4, SERVICE, RESET; VDD = 4.5 V-5.5 V 9
Input High Voltage VIH 2 V I/O0-I/O10, CP0, CP3, CP4, SERVICE, RESET; VDD = 4.5 V-5.5 V 9
Low-Level Output Voltage VOL 0.1 V Iout < 20 µA 9
Low-Level Output Voltage, standard outputs VOL 0.4 V Standard Outputs (IOL = 1.4 mA) 9
Low-Level Output Voltage, high sink VOL 0.8 V High Sink (I/O0-I/O3), SERVICE, RESET (IOL = 20 mA) 9
Low-Level Output Voltage, high sink VOL 0.4 V High Sink (I/O0-I/O3), SERVICE, RESET (IOL = 10 mA) 9
Low-Level Output Voltage, maximum sink VOL 1 V Maximum Sink (CP2, CP3) (IOL = 40 mA) 9
Low-Level Output Voltage, maximum sink VOL 0.4 V Maximum Sink (CP2, CP3) (IOL = 15 mA) 9
Hysteresis (Excluding CLK1) Vhys 175 mV 9
Input Current (Excluding Pull Ups) Iin -10 10 µA VSS to VDD 9
Pull Up Source Current Ipu 60 260 µA Vout = 0 V, Output = High-Z 9
Operating Mode Supply Current IDD 55 mA 40-MHz Clock 9
Operating Mode Supply Current IDD 32 mA 20-MHz Clock 9
Operating Mode Supply Current IDD 20 mA 10-MHz Clock 9
Operating Mode Supply Current IDD 12 mA 5-MHz Clock 9
Operating Mode Supply Current IDD 8 mA 2.5-MHz Clock 9
Operating Mode Supply Current IDD 7 mA 1.25-MHz Clock 9
Operating Mode Supply Current IDD 3 mA 0.625-MHz Clock 9
Sleep Mode Supply Current IDDsleep 100 µA 9
LVI Trip Point VDD 3.8 4.1 4.4 V CY7C53120E4 9
Supply Voltage VDD 4.5 5 5.5 V Electrical Characteristics (VDD = 4.5 V-5.5 V); 5 V nom 9
Receiver Common Mode Voltage Range to maintain hysteresis 1.2 V Max is VDD - 2.2 10
Receiver Common Mode Range to operate with unspecified hysteresis 0.9 V Max is VDD - 1.75 10
Propagation Delay 230 ns F = 0, VID = Vhys/2 + 200 mV 10
Input Resistance 5 MΩ 10
Wake-up Time 10 µs 10
Glitch Filter Pulse Suppression Time 10 75 140 ns Filter F = 0 8
Glitch Filter Pulse Suppression Time 120 410 700 ns Filter F = 1 8
Glitch Filter Pulse Suppression Time 240 800 1350 ns Filter F = 2 8
Glitch Filter Pulse Suppression Time 480 1500 2600 ns Filter F = 3 8
Receiver Absolute Asymmetry tPLH, tPHL 35 ns Filter F = 0, worst case across hysteresis 8
Receiver Absolute Asymmetry tPLH, tPHL 150 ns Filter F = 1, worst case across hysteresis 8
Receiver Absolute Asymmetry tPLH, tPHL 250 ns Filter F = 2, worst case across hysteresis 8
Receiver Absolute Asymmetry tPLH, tPHL 400 ns Filter F = 3, worst case across hysteresis 8
Differential Receiver Absolute Symmetry tPLH, tPHL 24 ns Filter F = 0, Hysteresis H = 0 8
Maximum Input Clock 40 MHz CY7C53120E4, -40°C to 85°C 1
Operating Temperature Range TA -40 85 °C 1
Maximum Junction Temperature TJ 105 °C 1
Thermal Resistance Junction to Ambient θJA 43 °C/W 44-pin TQFP 1

CAD (KiCad official)

  • Symbol: CY7C53120E4-40AXI
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy7c53120e4-40axi-etched.step / cy7c53120e4-40axi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy7c53120e4-40axi.step / cy7c53120e4-40axi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (19 pp, sha256 78effbe30b11228d, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF