main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers cy74fct821ctqct: viewers · Ray 1d ago
cy74fct821ctqct-etched.glb cy74fct821ctqct: factory component page (tier=lcsc) · Ray 1d ago
cy74fct821ctqct-etched.step cy74fct821ctqct: factory component page (tier=lcsc) · Ray 1d ago
cy74fct821ctqct-hero.glb cy74fct821ctqct: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
cy74fct821ctqct-hero.overlay.json Publish 0.1.0 · Ray 1d ago
cy74fct821ctqct.glb Publish 0.1.0 · Ray 1d ago
cy74fct821ctqct.kicad_mod Publish 0.1.0 · Ray 1d ago
cy74fct821ctqct.kicad_sym Publish 0.1.0 · Ray 1d ago
cy74fct821ctqct.lbr Publish 0.1.0 · Ray 1d ago
cy74fct821ctqct.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/cy74fct821ctqct · Ray 1d ago

CY74FCT821CTQCT

Texas Instruments · Flip Flops · QSOP-24-150mil

CY74FCT821CTQCT from Texas Instruments, in a QSOP-24-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output enable: when OE is high the Y outputs are forced to the high-impedance state, and when OE is low the true register data is present at the Y outputs.
2 D0 input D flip-flop data input 0, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
3 D1 input D flip-flop data input 1, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
4 D2 input D flip-flop data input 2, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
5 D3 input D flip-flop data input 3, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
6 D4 input D flip-flop data input 4, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
7 D5 input D flip-flop data input 5, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
8 D6 input D flip-flop data input 6, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
9 D7 input D flip-flop data input 7, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
10 D8 input D flip-flop data input 8, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
11 D9 input D flip-flop data input 9, captured on the low-to-high transition of CP; the datasheet gives VIH min 2 V and VIL max 0.8 V for inputs.
12 GND power_in Ground reference for the device.
13 CP input Clock pulse for the register: data is entered into the register on the low-to-high clock transition; CT minimum pulse duration is 6 ns.
14 Y9 tri_state Register 3-state output 9, high-impedance when OE is high.
15 Y8 tri_state Register 3-state output 8, high-impedance when OE is high.
16 Y7 tri_state Register 3-state output 7, high-impedance when OE is high.
17 Y6 tri_state Register 3-state output 6, high-impedance when OE is high.
18 Y5 tri_state Register 3-state output 5, high-impedance when OE is high.
19 Y4 tri_state Register 3-state output 4, high-impedance when OE is high.
20 Y3 tri_state Register 3-state output 3, high-impedance when OE is high.
21 Y2 tri_state Register 3-state output 2, high-impedance when OE is high.
22 Y1 tri_state Register 3-state output 1, high-impedance when OE is high.
23 Y0 tri_state Register 3-state output 0, high-impedance when OE is high; the datasheet specifies IOL up to 64 mA and IOH up to -32 mA for the outputs.
24 VCC power_in Supply voltage, 4.75 V minimum to 5.25 V maximum (5 V nominal).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QSOP-24-150mil
Category Logic
Pins 24

CAD (KiCad official)

  • Symbol: CY74FCT821CTQCT
  • Footprint: Package_SO:QSOP-24_3.9x8.7mm_P0.635mm
  • 3D model: QSOP-24-150mil (KiCad packages3D, STEP)
  • 3D model files: cy74fct821ctqct-etched.step / cy74fct821ctqct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy74fct821ctqct.step / cy74fct821ctqct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 5826866e972c5a41, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF