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CY74FCT2541ATSOC

Texas Instruments · Buffer/Driver/Transceiver · SOIC-20-300mil

CY74FCT2541ATSOC from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OEA input Output enable A control input that gates the outputs together with OEB, per the function table on page 2; the datasheet gives no separate electrical limit for this pin beyond the TTL VIH and VIL levels.
2 D0 input Data input to buffer channel 0 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
3 D1 input Data input to buffer channel 1 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
4 D2 input Data input to buffer channel 2 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
5 D3 input Data input to buffer channel 3 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
6 D4 input Data input to buffer channel 4 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
7 D5 input Data input to buffer channel 5 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
8 D6 input Data input to buffer channel 6 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
9 D7 input Data input to buffer channel 7 with TTL-compatible levels, VIH minimum 2 V and VIL maximum 0.8 V.
10 GND power_in Ground reference for the device; the datasheet states supply voltage range from 4.75 V to 5.25 V with respect to ground.
11 O7 tri_state 3-state buffer output channel 7 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
12 O6 tri_state 3-state buffer output channel 6 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
13 O5 tri_state 3-state buffer output channel 5 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
14 O4 tri_state 3-state buffer output channel 4 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
15 O3 tri_state 3-state buffer output channel 3 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
16 O2 tri_state 3-state buffer output channel 2 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
17 O1 tri_state 3-state buffer output channel 1 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
18 O0 tri_state 3-state buffer output channel 0 with 25 Ω series termination, sourcing up to 15 mA (IOH) and sinking up to 12 mA (IOL).
19 OEB input Output enable B control input that gates the outputs together with OEA, per the function table on page 2; the datasheet gives no separate electrical limit for this pin beyond the TTL VIH and VIL levels.
20 VCC power_in Positive supply input; the datasheet specifies VCC of 4.75 V minimum, 5 V nominal and 5.25 V maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V 3
High-level input voltage VIH 2 V 3
Low-level input voltage VIL 0.8 V 3
High-level output current IOH -15 mA 3
Low-level output current IOL 12 mA 3
Operating free-air temperature TA -40 85 °C 3
Supply voltage range to ground potential VCC -0.5 7 V 2
DC input voltage range VI -0.5 7 V 2
DC output voltage range VO -0.5 7 V 2
DC output current (maximum sink current/pin) IO 120 mA 2
Ambient temperature range with power applied TA -65 135 °C 2
Storage temperature range Tstg -65 150 °C 2
Package thermal impedance, SO package θJA 58 °C/W SO package, JESD 51-7 2
Input clamp voltage VIK -0.7 -1.2 V VCC = 4.75 V, IIN = -18 mA 4
High-level output voltage VOH 2.4 3.3 V VCC = 4.75 V, IOH = -15 mA 4
Low-level output voltage VOL 0.3 0.55 V VCC = 4.75 V, IOL = 12 mA 4
Output resistance Rout 20 25 40 Ω VCC = 4.75 V, IOL = 12 mA 4
Input hysteresis Vhys 0.2 V All inputs 4
Input current II 5 µA VCC = 5.25 V, VIN = VCC 4
High-level input current IIH -1 1 µA VCC = 5.25 V, VIN = 2.7 V 4
Low-level input current IIL -1 1 µA VCC = 5.25 V, VIN = 0.5 V 4
Off-state output current, high-level voltage applied IOZH 15 µA VCC = 5.25 V, VOUT = 2.7 V 4
Off-state output current, low-level voltage applied IOZL -15 µA VCC = 5.25 V, VOUT = 0.5 V 4
Short-circuit output current IOS -60 -120 -225 mA VCC = 5.25 V, VOUT = 0 V 4
Power-off leakage current Ioff -1 1 µA VCC = 0 V, VOUT = 4.5 V 4
Quiescent supply current ICC 0.1 0.2 mA VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC, 0.2 V 4
Supply current per TTL high input ΔICC 0.5 2 mA VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open 4
Dynamic current per MHz ICCD 0.06 0.12 mA/MHz VCC = 5.25 V at 50% duty cycle, Outputs open, One bit switching, OEA = OEB = GND, VIN ≤ 0.2 V or VIN≥VCC, 0.2 V 4
Input capacitance Ci 5 10 pF 4
Output capacitance Co 9 12 pF 4
Propagation delay D to O (tPLH) tPLH 1.5 4.8 ns see Figure 1 5
Propagation delay D to O (tPHL) tPHL 1.5 4.8 ns see Figure 1 5
Enable time OE to O (tPZH) tPZH 1.5 6.2 ns see Figure 1 5
Enable time OE to O (tPZL) tPZL 1.5 6.2 ns see Figure 1 5
Disable time OE to O (tPHZ) tPHZ 1.5 5.6 ns see Figure 1 5
Disable time OE to O (tPLZ) tPLZ 1.5 5.6 ns see Figure 1 5

CAD (KiCad official)

  • Symbol: CY74FCT2541ATSOC
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: cy74fct2541atsoc-etched.step / cy74fct2541atsoc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy74fct2541atsoc.step / cy74fct2541atsoc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 98c9563c617955be, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF