main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers cy74fct244atpc: viewers · Ray 4d ago
cy74fct244atpc-etched.glb Publish 0.1.0 · Ray 4d ago
cy74fct244atpc-etched.step cy74fct244atpc: factory component page (tier=mfr) · Ray 4d ago
cy74fct244atpc-hero.glb cy74fct244atpc: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
cy74fct244atpc-hero.overlay.json Publish 0.1.0 · Ray 4d ago
cy74fct244atpc.glb Publish 0.1.0 · Ray 4d ago
cy74fct244atpc.kicad_mod Publish 0.1.0 · Ray 4d ago
cy74fct244atpc.kicad_sym Publish 0.1.0 · Ray 4d ago
cy74fct244atpc.lbr Publish 0.1.0 · Ray 4d ago
cy74fct244atpc.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago

CY74FCT244ATPC

Texas Instruments · Buffers / Drivers · PDIP-20

CY74FCT244ATPC from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OEA input Output enable for the A bank, active low; when OEA is high the OA0-OA3 outputs are in the high-impedance state.
2 DA0 input Data input A0 that drives output OA0 (TTL-compatible; unused inputs must be held at VCC or GND).
3 OB0 tri_state 3-state output B0 that follows DB0, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
4 DA1 input Data input A1 that drives output OA1 (TTL-compatible; unused inputs must be held at VCC or GND).
5 OB1 tri_state 3-state output B1 that follows DB1, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
6 DA2 input Data input A2 that drives output OA2 (TTL-compatible; unused inputs must be held at VCC or GND).
7 OB2 tri_state 3-state output B2 that follows DB2, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
8 DA3 input Data input A3 that drives output OA3 (TTL-compatible; unused inputs must be held at VCC or GND).
9 OB3 tri_state 3-state output B3 that follows DB3, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
10 GND power_in Ground.
11 DB3 input Data input B3 that drives output OB3 (TTL-compatible; unused inputs must be held at VCC or GND).
12 OA3 tri_state 3-state output A3 that follows DA3, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
13 DB2 input Data input B2 that drives output OB2 (TTL-compatible; unused inputs must be held at VCC or GND).
14 OA2 tri_state 3-state output A2 that follows DA2, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
15 DB1 input Data input B1 that drives output OB1 (TTL-compatible; unused inputs must be held at VCC or GND).
16 OA1 tri_state 3-state output A1 that follows DA1, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
17 DB0 input Data input B0 that drives output OB0 (TTL-compatible; unused inputs must be held at VCC or GND).
18 OA0 tri_state 3-state output A0 that follows DA0, with 64-mA sink and 32-mA source output drive for CY74FCT244T.
19 OEB input Output enable for the B bank, active low; when OEB is high the OB0-OB3 outputs are in the high-impedance state.
20 VCC power_in Supply voltage, 4.75 V to 5.25 V recommended for CY74FCT244T (absolute maximum -0.5 V to 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V CY74FCT244T 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
High-level output current IOH -32 mA 4
Low-level output current IOL 64 mA 4
Operating free-air temperature TA -40 85 °C 4
Supply voltage range VCC -0.5 7 V to ground potential 3
DC input voltage range VI -0.5 7 V 3
DC output voltage range VO -0.5 7 V 3
DC output current 120 mA maximum sink current/pin 3
Ambient temperature range with power applied TA -65 135 °C 3
Storage temperature range Tstg -65 150 °C 3
Package thermal impedance, P package θJA 69 °C/W P package, JESD 51-7 3
Input clamp voltage VIK -0.7 -1.2 V VCC = 4.75 V, IIN = -18 mA 5
High-level output voltage VOH 2 V VCC = 4.75 V, IOH = -32 mA 5
High-level output voltage VOH 2.4 3.3 V VCC = 4.75 V, IOH = -15 mA 5
Low-level output voltage VOL 0.3 0.55 V VCC = 4.75 V, IOL = 64 mA 5
Input hysteresis Vhys 0.2 V All inputs 5
Input current II 5 µA VCC = 5.25 V, VIN = VCC 5
High-level input current IIH -1 1 µA VCC = 5.25 V, VIN = 2.7 V 5
Low-level input current IIL -1 1 µA VCC = 5.25 V, VIN = 0.5 V 5
Off-state output current (high) IOZH 10 µA VCC = 5.25 V, VOUT = 2.7 V 5
Off-state output current (low) IOZL -10 µA VCC = 5.25 V, VOUT = 0.5 V 5
Short-circuit output current IOS -60 -120 -225 mA VCC = 5.25 V, VOUT = 0 V 5
Partial-power-down output current Ioff -1 1 µA VCC = 0 V, VOUT = 4.5 V 5
Supply current ICC 0.1 0.2 mA VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC, 0.2 V 5
Supply current increase per TTL input ∆ICC 0.5 2 mA VCC = 5.25 V, VIN = 3.4 V, f1 = 0, Outputs open 5
Dynamic supply current ICCD 0.06 0.12 mA/MHz VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, OEA = OEB = GND, VIN ≤ 0.2 V or VIN ≥ VCC, 0.2 V 5
Total supply current, one bit switching, CMOS levels IC 0.7 1.4 mA VCC = 5.25 V, one bit at f1 = 10 MHz, 50% duty cycle, VIN ≤ 0.2 V or VIN ≥ VCC, 0.2 V, Outputs open, OEA = OEB = GND 6
Total supply current, one bit switching, TTL levels IC 1 2.4 mA VCC = 5.25 V, one bit at f1 = 10 MHz, 50% duty cycle, VIN = 3.4 V or GND, Outputs open, OEA = OEB = GND 6
Total supply current, eight bits switching, CMOS levels IC 1.3 2.6 mA VCC = 5.25 V, eight bits at f1 = 2.5 MHz, 50% duty cycle, VIN = 0.2 V or VIN ≥ VCC, 0.2 V, Outputs open, OEA = OEB = GND 6
Total supply current, eight bits switching, TTL levels IC 3.3 10.6 mA VCC = 5.25 V, eight bits at f1 = 2.5 MHz, 50% duty cycle, VIN = 3.4 V or GND, Outputs open, OEA = OEB = GND 6
Propagation delay, D to O (low-to-high) tPLH 1.5 4.6 ns CY74FCT244AT, D to O 7
Propagation delay, D to O (high-to-low) tPHL 1.5 4.6 ns CY74FCT244AT, D to O 7
Output enable time to high level tPZH 1.5 6.2 ns CY74FCT244AT, OE to O 7
Output enable time to low level tPZL 1.5 6.2 ns CY74FCT244AT, OE to O 7
Output disable time from high level tPHZ 1.5 5.6 ns CY74FCT244AT, OE to O 7
Output disable time from low level tPLZ 1.5 5.6 ns CY74FCT244AT, OE to O 7
Input capacitance Ci 5 10 pF 6
Output capacitance Co 9 12 pF 6

CAD (KiCad official)

  • Symbol: CY74FCT244ATPC
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: cy74fct244atpc-etched.step / cy74fct244atpc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy74fct244atpc.step / cy74fct244atpc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 b3e7a137db22363a, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF