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CY62148ELL-45ZSXI

Public Made by Adom

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Cypress Semicon Pre-ordered Products, SOIC-32. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy62148ell-45zsxifactory-2.0.0extractor-text

Verified CY62148ELL-45ZSXI

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 32 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY62148ELL-45ZSXI · SOIC-32 · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 20-page datasheet
  • ✓distributor: lcsc C2947424, digikey 448-CY62148ELL-45ZSXI-ND, mouser 727-CY6218ELL-45ZSXI
  • ✓family: SOIC-32_7.518x20.777mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-05vel1sf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy62148ell-45zsxi.kicad_sym✓ cy62148ell-45zsxi.kicad_mod✓ cy62148ell-45zsxi.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray
viewers cy62148ell-45zsxi: viewers · Ray
cy62148ell-45zsxi-etched.glb Publish 0.1.0 · Ray
cy62148ell-45zsxi-etched.step cy62148ell-45zsxi: factory component page (tier=lcsc) · Ray
cy62148ell-45zsxi-hero.glb cy62148ell-45zsxi: hero GLB from the etched model (keeps the MPN mark) · Ray
cy62148ell-45zsxi-hero.overlay.json Publish 0.1.0 · Ray
cy62148ell-45zsxi.glb Publish 0.1.0 · Ray
cy62148ell-45zsxi.kicad_mod Publish 0.1.0 · Ray
cy62148ell-45zsxi.kicad_sym Publish 0.1.0 · Ray
cy62148ell-45zsxi.lbr Publish 0.1.0 · Ray
cy62148ell-45zsxi.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 32 pins · Ray

CY62148ELL-45ZSXI

Cypress Semicon · Pre-ordered Products · SOIC-32

CY62148ELL-45ZSXI from Cypress Semicon, in a SOIC-32. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A17 input Address input A17 selecting the memory location, one of A0 through A18.
2 A16 input Address input A16 selecting the memory location, one of A0 through A18.
3 A14 input Address input A14 selecting the memory location, one of A0 through A18.
4 A12 input Address input A12 selecting the memory location, one of A0 through A18.
5 A7 input Address input A7 selecting the memory location, one of A0 through A18.
6 A6 input Address input A6 selecting the memory location, one of A0 through A18.
7 A5 input Address input A5 selecting the memory location, one of A0 through A18.
8 A4 input Address input A4 selecting the memory location, one of A0 through A18.
9 A3 input Address input A3 selecting the memory location, one of A0 through A18.
10 A2 input Address input A2 selecting the memory location, one of A0 through A18.
11 A1 input Address input A1 selecting the memory location, one of A0 through A18.
12 A0 input Address input A0 selecting the memory location, one of A0 through A18.
13 I/O0 bidirectional Data input/output 0; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
14 I/O1 bidirectional Data input/output 1; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
15 I/O2 bidirectional Data input/output 2; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
16 VSS power_in Ground for the device.
17 I/O3 bidirectional Data input/output 3; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
18 I/O4 bidirectional Data input/output 4; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
19 I/O5 bidirectional Data input/output 5; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
20 I/O6 bidirectional Data input/output 6; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
21 I/O7 bidirectional Data input/output 7; high impedance when deselected (CE HIGH), outputs disabled (OE HIGH), or during a write.
22 CE input Chip Enable, active LOW; HIGH deselects the device and places it in standby power-down.
23 A10 input Address input A10 selecting the memory location, one of A0 through A18.
24 OE input Output Enable, active LOW; taken LOW with CE LOW and WE HIGH to read data onto the I/O pins.
25 A11 input Address input A11 selecting the memory location, one of A0 through A18.
26 A9 input Address input A9 selecting the memory location, one of A0 through A18.
27 A8 input Address input A8 selecting the memory location, one of A0 through A18.
28 A13 input Address input A13 selecting the memory location, one of A0 through A18.
29 WE input Write Enable, active LOW; taken LOW with CE LOW to write I/O data into the addressed location.
30 A18 input Address input A18 selecting the memory location, one of A0 through A18.
31 A15 input Address input A15 selecting the memory location, one of A0 through A18.
32 VCC power_in Supply voltage, 4.5 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-32
Category Electronic Tools/Instruments/Consumables
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output HIGH voltage VOH 2.4 V VCC = 4.5 V, IOH = -1 mA 5
Output HIGH voltage VOH 3.4 V VCC = 5.5 V, IOH = -0.1 mA 5
Output LOW voltage VOL 0.4 V IOL = 2.1 mA 5
Input HIGH voltage VIH 2.2 V VCC = 4.5 V to 5.5 V; printed max is VCC + 0.5 5
Input LOW voltage (TSOP II package) VIL -0.5 0.8 V VCC = 4.5 V to 5.5 V; TSOP II package 5
Input leakage current IIX -1 1 µA GND < VI < VCC 5
Output leakage current IOZ -1 1 µA GND < VO < VCC, output disabled 5
VCC operating supply current ICC 15 20 mA f = fmax = 1/tRC, VCC = VCC(max), IOUT = 0 mA, CMOS levels 5
VCC operating supply current ICC 3.5 6 mA f = 1 MHz, VCC = VCC(max), IOUT = 0 mA, CMOS levels 5
Automatic CE power-down current, CMOS inputs ISB2 2.5 7 µA CE > VCC, 0.2 V, VIN > VCC, 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max) 5
VCC for data retention VDR 2 V 7
Data retention current ICCDR 3 8.8 µA VCC = VDR, CE > VCC, 0.2 V, VIN > VCC, 0.2 V or VIN < 0.2 V 7
Chip deselect to data retention time tCDR 0 ns 7
Operation recovery time tR 45 ns 45 ns speed bin (printed 45/55) 7
Read cycle time tRC 45 ns 8
Address to data valid tAA 45 ns 8
Data hold from address change tOHA 10 ns 8
CE LOW to data valid tACE 45 ns 8
OE LOW to data valid tDOE 22 ns 8
OE LOW to low Z tLZOE 5 ns 8
OE HIGH to high Z tHZOE 18 ns 8
CE LOW to low Z tLZCE 10 ns 8
CE HIGH to high Z tHZCE 18 ns 8
CE LOW to power-up tPU 0 ns 8
CE HIGH to power-down tPD 45 ns 8
Write cycle time tWC 45 ns 8
CE LOW to write end tSCE 35 ns 8
Address setup to write end tAW 35 ns 8
Address hold from write end tHA 0 ns 8
Address setup to write start tSA 0 ns 8
WE pulse width tPWE 35 ns 8
Data setup to write end tSD 25 ns 8
Data hold from write end tHD 0 ns 8
WE LOW to high Z tHZWE 18 ns 8
WE HIGH to low Z tLZWE 10 ns 8
Storage temperature TSTG -65 150 °C 5
Ambient temperature with power applied TA -55 125 °C 5
Supply voltage to ground potential -0.5 6 V printed as (VCCmax + 0.5 V) 5
DC voltage applied to outputs in high Z state -0.5 6 V printed as (VCCmax + 0.5 V); notes 4, 5 5
DC input voltage -0.5 6 V printed as (VCCmax + 0.5 V); notes 4, 5 5
Output current into outputs (LOW) 20 mA 5
Static discharge voltage (MIL-STD-883, Method 3015) 2001 V printed as > 2001 V 5
Latch-up current 200 mA printed as > 200 mA 5
Supply voltage VCC VCC 4.5 5 5.5 V Industrial/Automotive-A, CY62148E 5
Ambient temperature (operating range) TA -40 85 °C Industrial/Automotive-A 5
Input capacitance CIN 10 pF TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) 6
Output capacitance COUT 10 pF 6
Thermal resistance (junction to ambient), 32-pin TSOP II θJA 59.1 °C/W Still air, soldered on a 3 × 4.5 inch four-layer PCB 6
Thermal resistance (junction to case), 32-pin TSOP II θJC 12.19 °C/W 6

CAD (KiCad official)

  • Symbol: CY62148ELL-45ZSXI
  • Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
  • 3D model: SOIC-32, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cy62148ell-45zsxi-etched.step / cy62148ell-45zsxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy62148ell-45zsxi.step / cy62148ell-45zsxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (20 pp, sha256 609e28364a300e8e, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF