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CY62128EV30LL-45SXIT

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Cypress Semicon SRAM, SOIC-32. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY62128EV30LL-45SXIT

Cypress Semicon · SRAM · SOIC-32

CY62128EV30LL-45SXIT from Cypress Semicon, in a SOIC-32. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; NC pins are not connected on the die.
2 A16 input Address input A16, the most significant of address pins A0 to A16 selecting one of 128K locations.
3 A14 input Address input A14, part of address pins A0 to A16 selecting the memory location.
4 A12 input Address input A12, part of address pins A0 to A16 selecting the memory location.
5 A7 input Address input A7, part of address pins A0 to A16 selecting the memory location.
6 A6 input Address input A6, part of address pins A0 to A16 selecting the memory location.
7 A5 input Address input A5, part of address pins A0 to A16 selecting the memory location.
8 A4 input Address input A4, part of address pins A0 to A16 selecting the memory location.
9 A3 input Address input A3, part of address pins A0 to A16 selecting the memory location.
10 A2 input Address input A2, part of address pins A0 to A16 selecting the memory location.
11 A1 input Address input A1, part of address pins A0 to A16 selecting the memory location.
12 A0 input Address input A0, the least significant of address pins A0 to A16 selecting the memory location.
13 I/O0 bidirectional Data I/O0; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
14 I/O1 bidirectional Data I/O1; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
15 I/O2 bidirectional Data I/O2; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
16 GND power_in Ground.
17 I/O3 bidirectional Data I/O3; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
18 I/O4 bidirectional Data I/O4; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
19 I/O5 bidirectional Data I/O5; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
20 I/O6 bidirectional Data I/O6; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
21 I/O7 bidirectional Data I/O7; high impedance when deselected, when outputs are disabled (OE HIGH), or during a write.
22 CE1 input Chip enable 1, active LOW; with CE2 HIGH selects the device, and CE1 HIGH deselects it into standby.
23 A10 input Address input A10, part of address pins A0 to A16 selecting the memory location.
24 OE input Output enable, active LOW; taking it LOW with WE HIGH drives read data onto the I/O pins, and HIGH places outputs in high impedance.
25 A11 input Address input A11, part of address pins A0 to A16 selecting the memory location.
26 A9 input Address input A9, part of address pins A0 to A16 selecting the memory location.
27 A8 input Address input A8, part of address pins A0 to A16 selecting the memory location.
28 A13 input Address input A13, part of address pins A0 to A16 selecting the memory location.
29 WE input Write enable, active LOW; with CE1 LOW and CE2 HIGH, taking WE LOW writes I/O data into the addressed location.
30 CE2 input Chip enable 2, active HIGH; with CE1 LOW selects the device, and CE2 LOW deselects it into standby.
31 A15 input Address input A15, part of address pins A0 to A16 selecting the memory location.
32 VCC power_in Supply voltage, 2.2 V to 3.6 V operating range.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-32
Category Memory
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output HIGH voltage VOH 2 V IOH = -0.1 mA 4
Output HIGH voltage VOH 2.4 V IOH = -1.0 mA, VCC > 2.70 V 4
Output LOW voltage VOL 0.4 V IOL = 0.1 mA 4
Input HIGH voltage VIH 1.8 V VCC = 2.2 V to 2.7 V (max VCC + 0.3 V) 4
Input HIGH voltage VIH 2.2 V VCC = 2.7 V to 3.6 V (max VCC + 0.3 V) 4
Input LOW voltage VIL -0.3 0.6 V VCC = 2.2 V to 2.7 V 4
Input LOW voltage VIL -0.3 0.8 V VCC = 2.7 V to 3.6 V 4
Input leakage current IIX -1 1 µA GND < VI < VCC 4
Output leakage current IOZ -1 1 µA GND < VO < VCC, output disabled 4
VCC operating supply current ICC 11 16 mA f = fmax = 1/tRC, VCC = VCCmax, IOUT = 0 mA, CMOS levels 4
VCC operating supply current ICC 1.3 2 mA f = 1 MHz, VCC = VCCmax, IOUT = 0 mA, CMOS levels 4
Automatic CE power-down current, CMOS inputs ISB1 1 4 µA CE1 > VCC, 0.2 V, CE2 < 0.2 V, VIN > VCC, 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE and WE), VCC = 3.60 V 4
VCC for data retention VDR 1.5 V 6
Data retention current ICCDR 3 µA VCC = 1.5 V, CE1 > VCC, 0.2 V or CE2 < 0.2 V, VIN > VCC, 0.2 V or VIN < 0.2 V, Industrial 6
Input capacitance CIN 10 pF TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 5
Output capacitance COUT 10 pF TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 5
Thermal resistance (junction to ambient), 32-pin SOIC ΘJA 79.34 °C/W Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 5
Thermal resistance (junction to case), 32-pin SOIC ΘJC 18.49 °C/W Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 5
Chip deselect to data retention time tCDR 0 ns 6
Operation recovery time tR 45 ns 6
Read cycle time tRC 45 ns 7
Address to data valid tAA 45 ns 7
Data hold from address change tOHA 10 ns 7
CE LOW to data valid tACE 45 ns 7
OE LOW to data valid tDOE 22 ns 7
OE LOW to low Z tLZOE 5 ns 7
OE HIGH to high Z tHZOE 18 ns 7
CE LOW to low Z tLZCE 10 ns 7
CE HIGH to high Z tHZCE 18 ns 7
CE LOW to power-up tPU 0 ns 7
CE HIGH to power-down tPD 45 ns 7
Write cycle time tWC 45 ns 7
CE LOW to write end tSCE 35 ns 7
Address setup to write end tAW 35 ns 7
Address hold from write end tHA 0 ns 7
Address setup to write start tSA 0 ns 7
WE pulse width tPWE 35 ns 7
Data setup to write end tSD 25 ns 7
Data hold from write end tHD 0 ns 7
WE LOW to high Z tHZWE 18 ns 7
WE HIGH to low Z tLZWE 10 ns 7
Supply voltage range (operating) VCC 2.2 3.6 V Industrial 4
Ambient temperature (operating) TA -40 85 °C Industrial 4
Storage temperature -65 150 °C 4
Ambient temperature with power applied -55 125 °C 4
Output current into outputs (LOW) 20 mA 4
Static discharge voltage 2001 V MIL-STD-883, method 3015, > 2001 V 4
Latch-up current 200 mA > 200 mA 4

CAD (KiCad official)

  • Symbol: CY62128EV30LL-45SXIT
  • Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
  • 3D model: SOIC-32, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cy62128ev30ll-45sxit-etched.step / cy62128ev30ll-45sxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy62128ev30ll-45sxit.step / cy62128ev30ll-45sxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (19 pp, sha256 646e785a2d6d94d2, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF