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CY62128EV30LL-45SXI

Public Made by Adom

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Cypress Semicon Pre-ordered Products, SOIC-32. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy62128ev30ll-45sxifactory-2.0.0extractor-text

Verified CY62128EV30LL-45SXI

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 32 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY62128EV30LL-45SXI · SOIC-32 · 32 pins
  • ✓copper: 32 copper pads, none touching another net
  • ✓datasheet: all 32 pin names found in the 19-page datasheet
  • ✓distributor: lcsc C2953883, digikey 448-CY62128EV30LL-45SXI-ND, mouser 727-CY128EV30LL45SXI
  • ✓family: SOIC-32_7.518x20.777mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9zpc9v_h/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 32 pins = 32 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 32 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy62128ev30ll-45sxi.kicad_sym✓ cy62128ev30ll-45sxi.kicad_mod✓ cy62128ev30ll-45sxi.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy62128ev30ll-45sxi: viewers · Ray
cy62128ev30ll-45sxi-etched.glb Publish 0.1.0 · Ray
cy62128ev30ll-45sxi-etched.step cy62128ev30ll-45sxi: factory component page (tier=lcsc) · Ray
cy62128ev30ll-45sxi-hero.glb cy62128ev30ll-45sxi: hero GLB from the etched model (keeps the MPN mark) · Ray
cy62128ev30ll-45sxi-hero.overlay.json Publish 0.1.0 · Ray
cy62128ev30ll-45sxi.glb Publish 0.1.0 · Ray
cy62128ev30ll-45sxi.kicad_mod Publish 0.1.0 · Ray
cy62128ev30ll-45sxi.kicad_sym Publish 0.1.0 · Ray
cy62128ev30ll-45sxi.lbr Publish 0.1.0 · Ray
cy62128ev30ll-45sxi.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 32 pins · Ray

CY62128EV30LL-45SXI

Cypress Semicon · Pre-ordered Products · SOIC-32

CY62128EV30LL-45SXI from Cypress Semicon, in a SOIC-32. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; NC pins are not connected on the die.
2 A16 input Address input A16, the most significant of the address pins A0 through A16 that select one of 128K locations.
3 A14 input Address input A14, one of the address pins A0 through A16 that select the memory location.
4 A12 input Address input A12, one of the address pins A0 through A16 that select the memory location.
5 A7 input Address input A7, one of the address pins A0 through A16 that select the memory location.
6 A6 input Address input A6, one of the address pins A0 through A16 that select the memory location.
7 A5 input Address input A5, one of the address pins A0 through A16 that select the memory location.
8 A4 input Address input A4, one of the address pins A0 through A16 that select the memory location.
9 A3 input Address input A3, one of the address pins A0 through A16 that select the memory location.
10 A2 input Address input A2, one of the address pins A0 through A16 that select the memory location.
11 A1 input Address input A1, one of the address pins A0 through A16 that select the memory location.
12 A0 input Address input A0, the least significant of the address pins A0 through A16 that select the memory location.
13 I/O0 bidirectional Data input/output 0, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
14 I/O1 bidirectional Data input/output 1, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
15 I/O2 bidirectional Data input/output 2, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
16 GND power_in Ground reference for the device.
17 I/O3 bidirectional Data input/output 3, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
18 I/O4 bidirectional Data input/output 4, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
19 I/O5 bidirectional Data input/output 5, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
20 I/O6 bidirectional Data input/output 6, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
21 I/O7 bidirectional Data input/output 7, which goes high impedance when the device is deselected, the outputs are disabled (OE HIGH), or a write is in progress.
22 CE1 input Active-LOW chip enable 1; the device is selected when CE1 is LOW and CE2 is HIGH, and CE1 HIGH deselects it into standby.
23 A10 input Address input A10, one of the address pins A0 through A16 that select the memory location.
24 OE input Active-LOW output enable; OE LOW enables the I/O outputs during a read, and OE HIGH places them in high impedance.
25 A11 input Address input A11, one of the address pins A0 through A16 that select the memory location.
26 A9 input Address input A9, one of the address pins A0 through A16 that select the memory location.
27 A8 input Address input A8, one of the address pins A0 through A16 that select the memory location.
28 A13 input Address input A13, one of the address pins A0 through A16 that select the memory location.
29 WE input Active-LOW write enable; WE LOW with CE1 LOW and CE2 HIGH writes the I/O data to the addressed location, and WE HIGH is required for a read.
30 CE2 input Active-HIGH chip enable 2; the device is selected when CE2 is HIGH and CE1 is LOW, and CE2 LOW deselects it into standby.
31 A15 input Address input A15, one of the address pins A0 through A16 that select the memory location.
32 VCC power_in Positive supply voltage, operating range 2.2 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-32
Category Electronic Tools/Instruments/Consumables
Pins 32

CAD (KiCad official)

  • Symbol: CY62128EV30LL-45SXI
  • Footprint: Package_SO:SOIC-32_7.518x20.777mm_P1.27mm
  • 3D model: SOIC-32, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cy62128ev30ll-45sxi-etched.step / cy62128ev30ll-45sxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy62128ev30ll-45sxi.step / cy62128ev30ll-45sxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (19 pp, sha256 1e905ea887a93cbe, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF