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CY2305SXC-1T

Public Made by Adom

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Cypress Semicon Clock Buffers, Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingcy2305sxc-1tfactory-2.0.0extractor-text

Verified CY2305SXC-1T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY2305SXC-1T · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C511128, digikey 448-CY2305SXC-1TTR-ND, mouser 727-CY2305SXC-1T
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-vn6vonmc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy2305sxc-1t.kicad_sym✓ cy2305sxc-1t.kicad_mod✓ cy2305sxc-1t.step
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Ray Publish 0.1.0 5a9d288

CY2305SXC-1T

Cypress Semicon · Clock Buffers, Drivers · SOIC-8

CY2305SXC-1T from Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Input reference frequency that the on-chip PLL locks to; 5-V tolerant input with a weak pull-down and a threshold of VDD/2.
2 CLK2 output Buffered clock output with a weak pull-down.
3 CLK1 output Buffered clock output with a weak pull-down.
4 GND power_in Ground supply pin.
5 CLK3 output Buffered clock output with a weak pull-down.
6 VDD power_in 3.3-V supply; the operating supply range is 3.0 V to 3.6 V.
7 CLK4 output Buffered clock output with a weak pull-down.
8 CLKOUT output Buffered clock output that also serves as the internal PLL feedback pin; for zero input-output delay its load must equal the other outputs' load.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-8
Category Clock and Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage to ground potential -0.5 7 V 6
DC input voltage (except REF) -0.5 V Max printed as VDD + 0.5 V (not numeric) 6
DC input voltage REF -0.5 7 V 6
Storage temperature -65 150 °C 6
Junction temperature 150 °C 6
Static discharge voltage 2000 V Per MIL-STD-883 Method 3015; printed as > 2,000 V 6
Supply voltage VDD 3 3.6 V Commercial (CY2305SC-XX/SXC-XX) 6
Operating temperature (ambient) TA 0 70 °C Commercial 6
Load capacitance, below 100 MHz CL 30 pF Below 100 MHz 6
Load capacitance, 100 MHz to 133 MHz CL 10 pF From 100 MHz to 133 MHz 6
Input capacitance CIN 7 pF 6
Power-up time for all VDDs to reach minimum specified voltage tPU 0.05 50 ms Power ramps must be monotonic 6
Input LOW voltage VIL 0.8 V 6
Input HIGH voltage VIH 2 V 6
Input LOW current IIL 50 µA VIN = 0 V 6
Input HIGH current IIH 100 µA VIN = VDD 6
Output LOW voltage VOL 0.4 V IOL = 8 mA (-1) 6
Output HIGH voltage VOH 2.4 V IOH = -8 mA (-1) 6
Power-down supply current IDD (PD mode) 12 µA REF = 0 MHz 6
Supply current IDD 32 mA Unloaded outputs at 66.67 MHz, SEL inputs at VSS 6
Output frequency t1 10 100 MHz 30-pF load 11
Output frequency t1 10 133.33 MHz 10-pF load 11
Duty cycle tDC 40 50 60 % Measured at 1.4 V, Fout = 66.67 MHz 11
Rise time t3 2.5 ns Measured between 0.8 V and 2.0 V 11
Fall time t4 2.5 ns Measured between 0.8 V and 2.0 V 11
Output-to-output skew t5 85 250 ps All outputs equally loaded 11
Delay, REF rising edge to CLKOUT rising edge t6A -350 0 350 ps Measured at VDD/2 11
Device-to-device skew t7 700 ps Measured at VDD/2 on the CLKOUT pins of devices 11
Cycle-to-cycle jitter tJ 70 200 ps Measured at 66.67 MHz, loaded outputs 11
PLL lock time tLOCK 1 ms Stable power supply, valid clock presented on REF pin 11
Thermal resistance, junction to ambient (8-pin SOIC) θJA 140 °C/W Per EIA/JESD51 8
Thermal resistance, junction to case (8-pin SOIC) θJC 54 °C/W 8

CAD (KiCad official)

  • Symbol: CY2305SXC-1T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cy2305sxc-1t-etched.step / cy2305sxc-1t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy2305sxc-1t.step / cy2305sxc-1t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (25 pp, sha256 14073478d440b5cc, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF