CY2305CSXI-1HT

{
  "slug": "cy2305csxi-1ht",
  "version": "0.1.0",
  "type": "component",
  "description": "Cypress Semicon Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "rtc-clock chip",
    "cy2305csxi-1ht",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cy2305csxi-1ht.kicad_sym",
    "cy2305csxi-1ht.kicad_mod",
    "cy2305csxi-1ht.glb",
    "cy2305csxi-1ht.step",
    "cy2305csxi-1ht.lbr",
    "docs/hero.png",
    "docs/cy2305csxi-1ht-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cy2305csxi-1ht-hero.glb",
    "cy2305csxi-1ht-hero.overlay.json",
    "cy2305csxi-1ht-etched.glb"
  ],
  "component": {
    "mpn": "CY2305CSXI-1HT",
    "manufacturer": "Cypress Semicon",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "RTC/Clock Chip",
    "subcategory": "Clock Generators / Frequency Synthesizers / PLL",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/3243efd60b09b3f0a2a632f575c60d4b.pdf",
    "parts": {
      "symbol": "cy2305csxi-1ht.kicad_sym",
      "footprint": "cy2305csxi-1ht.kicad_mod",
      "model_3d": "cy2305csxi-1ht-hero.glb",
      "model_3d_plain": "cy2305csxi-1ht-etched.glb",
      "model_3d_step": "cy2305csxi-1ht-etched.step",
      "model_3d_step_plain": "cy2305csxi-1ht.step",
      "lbr": "cy2305csxi-1ht.lbr"
    },
    "distributor_links": {
      "lcsc": "C2952648",
      "digikey": "448-CY2305CSXI-1HTTR-ND",
      "mouser": "727-CY2305CSXI-1HT"
    },
    "distributor_check": {
      "checked_at": "2026-10-31T01:09:40Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "448-CY2305CSXI-1HTTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "727-CY2305CSXI-1HT",
        "status": "found",
        "lifecycle": "Not Recommended for New Designs"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "REF",
        "type": "input",
        "description": "Input reference frequency; the PLL locks to this clock input, which has a VDD/2 threshold and a weak pull-down."
      },
      {
        "number": "2",
        "name": "CLK2",
        "type": "output",
        "description": "Buffered clock output with a weak pull-down."
      },
      {
        "number": "3",
        "name": "CLK1",
        "type": "output",
        "description": "Buffered clock output with a weak pull-down."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground."
      },
      {
        "number": "5",
        "name": "CLK3",
        "type": "output",
        "description": "Buffered clock output with a weak pull-down."
      },
      {
        "number": "6",
        "name": "VDD",
        "type": "power_in",
        "description": "3.3 V supply; the datasheet operating range is 3.0 V to 3.6 V."
      },
      {
        "number": "7",
        "name": "CLK4",
        "type": "output",
        "description": "Buffered clock output with a weak pull-down."
      },
      {
        "number": "8",
        "name": "CLKOUT",
        "type": "output",
        "description": "Buffered clock output that is also the internal PLL feedback pin; its capacitive load must equal that of the other outputs for zero input-output delay."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The MPN CY2305CSXI-1HT is listed on page 15 as an 8-pin SOIC (150 Mil) Industrial Tape and Reel part; Pin descriptions were taken from the 8-pin SOIC table on page 5. The page 4 pinout figure text is sc; The datasheet gives VDD and temperature limits for the Industrial grade on page 7 (VDD 3.0 V to 3.6 "
        ],
        "pages_sent": 22,
        "cost_usd": 0.0673,
        "at": "2026-10-31T01:08:53"
      },
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/3243efd60b09b3f0a2a632f575c60d4b.pdf",
        "pages": 22,
        "sha256": "1e1eda0ba9771e9b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "cy2305csxi-1ht.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cy2305csxi-1ht-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "a4b74caf9a3f6d67a6cc903f85f2d3246a1cde952b7655778469410a6629ad78",
        "checked": "2026-10-31",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}