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CY2305CSXI-1HT

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Cypress Semicon Clock Generators / Frequency Synthesizers / PLL, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcy2305csxi-1htfactory-2.0.0extractor-text

Verified CY2305CSXI-1HT

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY2305CSXI-1HT · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 22-page datasheet
  • ✓distributor: lcsc C2952648, digikey 448-CY2305CSXI-1HTTR-ND, mouser 727-CY2305CSXI-1HT
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5_c3srhu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy2305csxi-1ht.kicad_sym✓ cy2305csxi-1ht.kicad_mod✓ cy2305csxi-1ht.step
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CY2305CSXI-1HT

Cypress Semicon · Clock Generators / Frequency Synthesizers / PLL · SOIC-8

CY2305CSXI-1HT from Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Input reference frequency; the PLL locks to this clock input, which has a VDD/2 threshold and a weak pull-down.
2 CLK2 output Buffered clock output with a weak pull-down.
3 CLK1 output Buffered clock output with a weak pull-down.
4 GND power_in Ground.
5 CLK3 output Buffered clock output with a weak pull-down.
6 VDD power_in 3.3 V supply; the datasheet operating range is 3.0 V to 3.6 V.
7 CLK4 output Buffered clock output with a weak pull-down.
8 CLKOUT output Buffered clock output that is also the internal PLL feedback pin; its capacitive load must equal that of the other outputs for zero input-output delay.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-8
Category RTC/Clock Chip
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 3 3.6 V Industrial / Automotive-A operating conditions table 7
Operating temperature (ambient temperature) TA -40 85 °C Industrial / Automotive-A operating conditions table 7
Load capacitance, below 100 MHz CL 30 pF below 100 MHz 7
Load capacitance, from 100 MHz to 133 MHz CL 10 pF from 100 MHz to 133 MHz 7
Input capacitance CIN 7 pF 7
Power-up time for all VDDs to reach minimum specified voltage tPU 0.05 50 ms power ramps are monotonic 7
Input LOW voltage VIL 0.8 V 8
Input HIGH voltage VIH 2 V 8
Input LOW current IIL 50 µA VIN = 0 V 8
Input HIGH current IIH 100 µA VIN = VDD 8
Output LOW voltage VOL 0.4 V IOL = 12 mA (-1H) 8
Output HIGH voltage VOH 2.4 V IOH = -12 mA (-1H) 8
Power-down supply current IDD (PD mode) 25 µA REF = 0 MHz 8
Supply current IDD 35 mA Unloaded outputs at 66.67 MHz, SEL inputs at VDD 8
Output frequency t1 10 100 MHz 30 pF load 13
Output frequency t1 10 133.33 MHz 10 pF load 13
Output duty cycle tDC 40 50 60 % Measured at 1.4 V, Fout > 50 MHz 13
Output duty cycle tDC 45 50 55 % Measured at 1.4 V, Fout < 50 MHz 13
Rise time t3 1.5 ns Measured between 0.8 V and 2.0 V 13
Fall time t4 1.5 ns Measured between 0.8 V and 2.0 V 13
Output-to-output skew t5 200 ps All outputs equally loaded 13
Delay, REF rising edge to CLKOUT rising edge t6A -350 0 350 ps Measured at VDD/2 13
Device-to-device skew t7 0 700 ps Measured at VDD/2 on the CLKOUT pins of devices 13
Output slew rate t8 1 V/ns Measured between 0.8 V and 2.0 V using Test circuit #2 13
Cycle-to-cycle jitter, peak tJ 175 ps Measured at 66.67 MHz, loaded outputs 13
PLL lock time tLOCK 1 ms Stable power supply, valid clock presented on REF pin 13
Supply voltage to ground potential -0.5 4.6 V 7
DC input voltage (Except REF) -0.5 V 7
DC input voltage REF -0.5 V 7
Storage temperature -65 150 °C 7
Junction temperature 150 °C 7
Static discharge voltage (per MIL-STD-883, Method 3015) 2000 V per MIL-STD-883, Method 3015 7
Thermal resistance, junction to ambient (8-pin SOIC) θJA 145 °C/W per EIA/JESD51 9
Thermal resistance, junction to case (8-pin SOIC) θJC 62 °C/W 9

CAD (KiCad official)

  • Symbol: CY2305CSXI-1HT
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cy2305csxi-1ht-etched.step / cy2305csxi-1ht-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy2305csxi-1ht.step / cy2305csxi-1ht.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (22 pp, sha256 1e1eda0ba9771e9b, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF