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Contents

README

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CY2305CSXC-1H

Cypress Semicon · Clock Generators / Frequency Synthesizers / PLL · SOIC-8

CY2305CSXC-1H from Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Input reference frequency pin with a weak pull-down; the PLL locks to the clock on this pin, which has a threshold of VDD/2.
2 CLK2 output Buffered clock output with a weak pull-down.
3 CLK1 output Buffered clock output with a weak pull-down.
4 GND power_in Ground supply pin.
5 CLK3 output Buffered clock output with a weak pull-down.
6 VDD power_in 3.3 V supply pin; operating supply voltage range is 3.0 V to 3.6 V.
7 CLK4 output Buffered clock output with a weak pull-down.
8 CLKOUT output Buffered clock output that also provides the internal PLL feedback; its load must equal the other outputs for zero delay.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-8
Category RTC/Clock Chip
Pins 8

CAD (KiCad official)

  • Symbol: CY2305CSXC-1H
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cy2305csxc-1h-etched.step / cy2305csxc-1h-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy2305csxc-1h.step / cy2305csxc-1h.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (22 pp, sha256 4c88d08d9298d52d, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF