# CY2305CSXC-1

**Cypress Semicon** · Real-time Clocks (RTC) · SOIC-8

CY2305CSXC-1 from Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | input | Input reference frequency that the on-chip PLL locks to; it has a weak pull-down and a threshold of VDD/2. |
| 2 | CLK2 | output | Buffered clock output with a weak pull-down; it is one of the five low-skew outputs driven from REF. |
| 3 | CLK1 | output | Buffered clock output with a weak pull-down; it is one of the five low-skew outputs driven from REF. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | CLK3 | output | Buffered clock output with a weak pull-down; it is one of the five low-skew outputs driven from REF. |
| 6 | VDD | power_in | 3.3 V supply; the datasheet specifies a supply range of 3.0 V to 3.6 V. |
| 7 | CLK4 | output | Buffered clock output with a weak pull-down; it is one of the five low-skew outputs driven from REF. |
| 8 | CLKOUT | output | Buffered clock output that also serves as the internal PLL feedback pin, so its loading must match the other outputs for zero delay; it has a weak pull-down. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SOIC-8 |
| Category | Clock and Timing |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 3 |  | 3.6 | V | Commercial temperature devices (CY2305CSXC-XX) | 7 |
| Operating temperature (ambient temperature) | TA | 0 |  | 70 | °C | Commercial temperature devices (CY2305CSXC-XX) | 7 |
| Load capacitance, below 100 MHz | CL |  |  | 30 | pF | Below 100 MHz | 7 |
| Load capacitance, from 100 MHz to 133 MHz | CL |  |  | 10 | pF | From 100 MHz to 133 MHz | 7 |
| Input capacitance | CIN |  |  | 7 | pF |  | 7 |
| Power-up time for all VDDs to reach minimum specified voltage (power ramps are monotonic) | tPU | 0.05 |  | 50 | ms | Power ramps are monotonic | 7 |
| Supply voltage to ground potential |  | -0.5 |  | 4.6 | V |  | 7 |
| DC input voltage (except REF), upper limit printed as VDD + 0.5 V |  | -0.5 |  |  | V | Upper limit printed as VDD + 0.5 V (not a fixed number) | 7 |
| DC input voltage REF, upper limit printed as VDD + 0.5 V |  | -0.5 |  |  | V | Upper limit printed as VDD + 0.5 V (not a fixed number) | 7 |
| Storage temperature |  | -65 |  | 150 | °C |  | 7 |
| Junction temperature |  |  |  | 150 | °C |  | 7 |
| Static discharge voltage |  | 2000 |  |  | V | Per MIL-STD-883, Method 3015; printed as > 2,000 V | 7 |
| Input LOW voltage | VIL |  |  | 0.8 | V |  | 8 |
| Input HIGH voltage | VIH | 2 |  |  | V |  | 8 |
| Input LOW current | IIL |  |  | 50 | µA | VIN = 0 V | 8 |
| Input HIGH current | IIH |  |  | 100 | µA | VIN = VDD | 8 |
| Output LOW voltage | VOL |  |  | 0.4 | V | IOL = 8 mA (-1) | 8 |
| Output HIGH voltage | VOH | 2.4 |  |  | V | IOH = -8 mA (-1) | 8 |
| Power-down supply current (PD mode) | IDD (PD mode) |  |  | 12 | µA | REF = 0 MHz | 8 |
| Supply current | IDD |  |  | 32 | mA | Unloaded outputs at 66.67 MHz, SEL inputs at VDD | 8 |
| Output frequency, 30 pF load | t1 | 10 |  | 100 | MHz | 30 pF load | 10 |
| Output frequency, 10 pF load | t1 | 10 |  | 133.33 | MHz | 10 pF load | 10 |
| Output duty cycle | tDC | 40 | 50 | 60 | % | Measured at 1.4 V, Fout > 50 MHz | 10 |
| Output duty cycle | tDC | 45 | 50 | 55 | % | Measured at 1.4 V, Fout 50 MHz (comparison symbol lost in text extraction) | 10 |
| Rise time | t3 |  |  | 2.25 | ns | Measured between 0.8 V and 2.0 V | 10 |
| Fall time | t4 |  |  | 2.25 | ns | Measured between 0.8 V and 2.0 V | 10 |
| Output-to-output skew | t5 |  |  | 200 | ps | All outputs equally loaded | 10 |
| Delay, REF rising edge to CLKOUT rising edge | t6A | -350 | 0 | 350 | ps | Measured at VDD/2 | 10 |
| Device-to-device skew | t7 |  | 0 | 700 | ps | Measured at VDD/2 on the CLKOUT pins of devices | 10 |
| Cycle-to-cycle jitter, peak | tJ |  | 50 | 175 | ps | Measured at 66.67 MHz, loaded outputs | 10 |
| PLL lock time | tLOCK |  |  | 1 | ms | Stable power supply, valid clock presented on REF pin | 10 |
| Thermal resistance, junction to ambient (8-pin SOIC) | θJA |  | 145 |  | °C/W | Per EIA/JESD51 test methods | 9 |
| Thermal resistance, junction to case (8-pin SOIC) | θJC |  | 62 |  | °C/W |  | 9 |

## CAD (KiCad official)

- Symbol: `CY2305CSXC-1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cy2305csxc-1-etched.step` / `cy2305csxc-1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy2305csxc-1.step` / `cy2305csxc-1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Cypress Semicon datasheet](docs/cy2305csxc-1-datasheet.pdf) (22 pp, sha256 `4c88d08d9298d52d`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cy2305csxc-1-datasheet.pdf)