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CY22393FXIT

Public Made by Adom

by adom

Infineon Clock Generators / Frequency Synthesizers / PLL, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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CY22393FXIT

Infineon · Clock Generators / Frequency Synthesizers / PLL · TSSOP-16

CY22393FXIT from Infineon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKC output Configurable clock output C. CMOS clock output routable from any of the three PLLs or the reference through the 4x4 crosspoint switch and 7-bit divider.
2 VDD power_in Digital 3.3 V power supply.
3 AGND power_in Analog ground for PLLs and crystal oscillator.
4 XTALIN input Reference crystal input or external reference clock input. Connect to one terminal of an 8-30 MHz crystal, or drive with an external 1-166 MHz reference clock.
5 XTALOUT output Reference crystal feedback. Connect to the second crystal terminal; leave floating when driving XTALIN with an external reference.
6 XBUF output Buffered reference clock output. CMOS-level replica of the reference (crystal or external) clock, enabled via Xbuf_OE.
7 CLKD output Configurable clock output D. CMOS clock output routable from any of the three PLLs or the reference through the 4x4 crosspoint switch and 7-bit divider.
8 CLKE output Configurable clock output E. CMOS clock output with a /2, /3, or /4 divider stage after the 4x4 crosspoint switch.
9 CLKB output Configurable clock output B. CMOS clock output routable from any of the three PLLs or the reference through the 4x4 crosspoint switch and 7-bit divider.
10 CLKA output Configurable clock output A. CMOS clock output routable from any of the three PLLs or the reference through the 4x4 crosspoint switch and 7-bit divider.
11 GND power_in Digital ground.
12 SDAT/S0 bidirectional Serial port data (two-wire serial interface). Doubles as a general-purpose frequency-select input: the S0 logic level is latched during start-up.
13 SCLK/S1 input Serial port clock (two-wire serial interface). Doubles as a general-purpose frequency-select input: the S1 logic level is latched during start-up.
14 AVDD power_in Analog 3.3 V power supply for the PLLs and crystal oscillator. Should be filtered from VDD for lowest jitter.
15 S2/SUSPEND input General-purpose frequency-select input (bit S2), latched at start-up. Optionally configurable as SUSPEND mode control input to place the device in low-power state.
16 SHUTDOWN/OE input Active-low SHUTDOWN or output-enable control. Default: LOW places all outputs in tristate and shuts down the chip. Optionally configurable as OE only: LOW tristates outputs without shutting down internal circuitry.

Key specifications

Parameter Value
Manufacturer Infineon
Package TSSOP-16
Category RTC
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • CY22393FXITZXC
  • CY22393FXITZXCT
  • CY22393FXITZXI
  • CY22393FXITZXIT
  • CY22393FXITFXC
  • CY22393FXITFXCT
  • CY22393FXIT

CAD (KiCad official)

  • Symbol: CY22393FXIT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cy22393fxit-etched.step / cy22393fxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy22393fxit.step / cy22393fxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon datasheet (27 pp, sha256 2f0310f940ea8fe3, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF