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CY22393FXE

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Cypress Semicon Pre-Ordered Products, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CY22393FXE

Cypress Semicon · Pre-Ordered Products · TSSOP-16

CY22393FXE from Cypress Semicon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKC output Configurable clock output C.
2 VDD power_in Power supply.
3 AGND power_in Analog ground.
4 XTALIN input Reference crystal input or external reference clock input; for driven clock inputs the on-die load capacitors can be bypassed to accept frequencies up to 166 MHz.
5 XTALOUT passive Reference crystal feedback; if the application uses a driven input, XTALOUT is to be left floating.
6 XBUF output Buffered reference clock output.
7 CLKD output Configurable clock output D.
8 CLKE output Configurable clock output E, which also carries the PLL1 output through a /2, /3, or /4 synchronous post-divider.
9 CLKB output Configurable clock output B.
10 CLKA output Configurable clock output A.
11 GND power_in Ground.
12 SDAT (S0) bidirectional Serial port data; the S0 value is latched during start-up and used as a frequency-select index.
13 SCLK (S1) input Serial port clock; the S1 value is latched during start-up and used as a frequency-select index.
14 AVDD power_in Analog power supply.
15 S2/SUSPEND input General-purpose input for frequency control (bit 2) that can optionally act as the Suspend mode control input.
16 SHUTDOWN/OE input Places outputs in tristate condition and shuts down the chip when LOW; optionally, it only places outputs in tristate and does not shut down the chip when LOW.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TSSOP-16
Category Electronic Tools/Instruments/Consumables
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD/AVDD 3.135 3.3 3.465 V 14
Automotive-E Grade operating temperature, ambient TA -40 125 °C Automotive-E Grade, ambient 14
Maximum load capacitance CLOAD_OUT 15 pF 14
External reference crystal frequency fREF 8 30 MHz External reference crystal 14
External reference clock frequency, Automotive fREF 1 150 MHz External reference clock, Automotive 14
Nominal crystal frequency FNOM 8 30 MHz Parallel resonance, fundamental mode 14
Nominal load capacitance CLNOM 8 20 pF 14
Equivalent series resistance (ESR) R1 50 Ω Fundamental mode 14
Crystal drive level DL 0.5 2 mW No external series resistor assumed 14
Supply voltage (absolute maximum) -0.5 7 V 14
DC input voltage -0.5 V Upper limit printed as AVDD + 0.5 V 14
Storage temperature -65 125 °C 14
Junction temperature, Automotive-E Grade TJ 150 °C Automotive-E Grade 14
Package power dissipation, Automotive-E Grade 217 mW Automotive-E Grade 14
Data retention 2 years TJ = 150 °C; printed as > 2 years 14
Maximum programming cycles 100 14
Static discharge voltage 2000 V Per MIL-STD-883, Method 3015; printed as > 2000 V 14
Latch-up -200 200 mA Per JEDEC 17; printed as > ±200 mA 14
Output high current IOH 12 24 mA VOH = VDD, 0.5 V, VDD = 3.3 V 15
Output low current IOL 12 24 mA VOL = 0.5 V, VDD = 3.3 V 15
High-level input voltage VIH 70 % of AVDD CMOS levels 15
Low-level input voltage VIL 30 % of AVDD CMOS levels 15
Input high current IIH 10 µA VIN = AVDD, 0.3 V 15
Input low current IIL 10 µA VIN = +0.3 V 15
Output leakage current IOZ 10 µA Three-state outputs (OE = Low) 15
Total power supply current in shutdown mode IDDS 5 20 µA Shutdown active 15
Output frequency 1/t1 166 MHz Clock output limit, CMOS, Automotive 16
Output duty cycle (Fout < 100 MHz, divider > 2) t2 45 50 55 % Fout < 100 MHz, divider > 2, measured at VDD/2 16
Output duty cycle (Fout > 100 MHz or divider = 1) t2 40 50 60 % Fout > 100 MHz or divider = 1, measured at VDD/2 16
Rising edge slew rate t3 0.75 1.4 V/ns Output clock rise time, 20% to 80% of VDD 16
Falling edge slew rate t4 0.75 1.4 V/ns Output clock fall time, 20% to 80% of VDD 16
Output three-state timing t5 150 300 ns Time for output to enter or leave three-state mode after SHUTDOWN/OE switches 16
Lock time t7 1 3 ms PLL lock time from power-up 16
Frequency of SCLK fSCLK 400 kHz 13
Hold time START condition tHD:STA 0.6 µs 13
Low period of the SCLK clock tLOW 1.3 µs 13
High period of the SCLK clock tHIGH 0.6 µs 13
Setup time for a repeated START condition tSU:STA 0.6 µs 13
Data hold time tHD:DAT 100 ns 13
Data setup time tSU:DAT 100 ns 13
Rise time tR 300 ns 13
Fall time tF 300 ns 13
Setup time for STOP condition tSU:STO 0.6 µs 13
Bus-free time between STOP and START conditions tBUF 1.3 µs 13
Package thermal resistance, junction to ambient JA 115 °C/W Package JA as stated in Junction Temperature Limitations 6

CAD (KiCad official)

  • Symbol: CY22393FXE
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cy22393fxe-etched.step / cy22393fxe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy22393fxe.step / cy22393fxe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (22 pp, sha256 829513a130aa9517, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF