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CY22393FXCT

Public Made by Adom

by adom

Cypress Semicon Pre-ordered Products, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY22393FXCT

Cypress Semicon · Pre-ordered Products · TSSOP-16

CY22393FXCT from Cypress Semicon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKC output Configurable clock output C, taken from the cross point switch through a programmable 7-bit post divider.
2 VDD power_in Power supply.
3 AGND power_in Analog ground.
4 XTALIN input Reference crystal input or external reference clock input.
5 XTALOUT passive Reference crystal feedback; leave floating when XTALIN is driven by an external clock.
6 XBUF output Buffered reference clock output.
7 CLKD output Configurable clock output D, taken from the cross point switch through a programmable 7-bit post divider.
8 CLKE output Configurable clock output E, derived from PLL1 through a post divider programmable to /2, /3, or /4.
9 CLKB output Configurable clock output B, whose 7-bit post divider is selected by S2 between two programmed register settings.
10 CLKA output Configurable clock output A, whose 7-bit post divider is selected by S2 between two programmed register settings.
11 GND power_in Ground.
12 SDAT (S0) bidirectional Serial port data; the S0 value is latched during start-up.
13 SCLK (S1) input Serial port clock; the S1 value is latched during start-up.
14 AVDD power_in Analog power supply.
15 S2/SUSPEND input General purpose input for frequency control (bit 2); optionally a suspend mode control input.
16 SHUTDOWN/OE input Places outputs in tristate and shuts down the chip when LOW; optionally, it only places outputs in tristate and does not shut down the chip when LOW.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TSSOP-16
Category Electronic Tools/Instruments/Consumables
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDD/AVDD/LVDD) VDD/AVDD/LVDD 3.135 3.3 3.465 V All parts 16
Commercial operating temperature, ambient TA 0 70 C Commercial 16
Maximum load capacitance CLOAD_OUT 15 pF All parts 16
External reference crystal frequency fREF 8 30 MHz External reference crystal 16
External reference clock frequency, commercial 1 166 MHz External reference clock, Commercial 16
Nominal crystal frequency FNOM 8 30 MHz Parallel resonance, fundamental mode 16
Nominal load capacitance CLNOM 8 20 pF 16
Equivalent series resistance (ESR) R1 50 Fundamental mode 16
Crystal drive level DL 0.5 2 mW No external series resistor assumed 16
Supply voltage -0.5 7 V 16
DC input voltage -0.5 V Upper limit printed as AVDD + 0.5 V 16
Storage temperature -65 125 C 16
Junction temperature 125 C 16
Data retention 10 years Tj = 125 C 16
Maximum programming cycles 100 16
Package power dissipation 350 mW 16
Static discharge voltage 2000 V Per MIL-STD-883, Method 3015; printed as > 2000 V 16
Latch up -200 200 mA Per JEDEC 17; printed as > ±200 mA 16
Output high current IOH 12 24 mA VOH = (L)VDD, 0.5, (L)VDD = 3.3 V 17
Output low current IOL 12 24 mA VOL = 0.5, (L)VDD = 3.3 V 17
High-level input voltage VIH 70 % of AVDD CMOS levels 17
Low-level input voltage VIL 30 % of AVDD CMOS levels 17
Input high current IIH 10 µA VIN = AVDD, 0.3 V 17
Input low current IIL 10 µA VIN = +0.3 V 17
Output leakage current IOZ 10 µA Three-state outputs 17
Total power supply current in shutdown mode IDDS 5 20 µA Shutdown active 17
Thermal resistance, junction to ambient θJA 90 °C/W 16-pin TSSOP, EIA/JESD51 test conditions 17
Thermal resistance, junction to case θJC 14 °C/W 16-pin TSSOP 17
Output frequency, CMOS commercial 1/t1 200 MHz Clock output limit, CMOS, Commercial 18
Output duty cycle (Fout < 100 MHz, divider >= 2) t2 45 50 55 % Defined as t2/t1, Fout < 100 MHz, divider >= 2, measured at VDD/2 18
Output duty cycle (Fout > 100 MHz or divider = 1) t2 40 50 60 % Defined as t2/t1, Fout > 100 MHz or divider = 1, measured at VDD/2 18
Rising edge slew rate t3 0.75 1.4 V/ns Output clock rise time, 20% to 80% of VDD 18
Falling edge slew rate t4 0.75 1.4 V/ns Output clock fall time, 20% to 80% of VDD 18
Output three-state timing t5 150 300 ns Time for output to enter or leave three-state mode after SHUTDOWN/OE switches 18
PLL lock time from power up t9 1 3 ms PLL lock time from power up 18

CAD (KiCad official)

  • Symbol: CY22393FXCT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cy22393fxct-etched.step / cy22393fxct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy22393fxct.step / cy22393fxct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (27 pp, sha256 2f0310f940ea8fe3, retrieved 2026-10-29, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF