CY22392FXIT

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  "slug": "cy22392fxit",
  "title": "CY22392FXIT",
  "brief": "Infineon Cypress Semicon Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "CY22392FXIT",
    "manufacturer": "Infineon Cypress Semicon",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Clock/Timing",
    "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120392822784",
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    "distributor_links": {
      "lcsc": "C2759946",
      "digikey": "448-CY22392FXITTR-ND",
      "mouser": "727-CY22392FXIT"
    },
    "distributor_check": {
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      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "448-CY22392FXITTR-ND",
        "status": "found",
        "lifecycle": "Active"
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        "pn": "727-CY22392FXIT",
        "status": "found",
        "lifecycle": "Not Recommended for New Designs"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CLKC",
        "type": "output",
        "description": "Configurable clock output C; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "2",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and all VDD pins must reach the specified voltage with monotonic ramps."
      },
      {
        "number": "3",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground; all grounds must be connected to the same ground plane."
      },
      {
        "number": "4",
        "name": "XTALIN",
        "type": "input",
        "description": "Reference crystal input or external reference clock input; crystal range is 8 MHz to 30 MHz, and an external reference clock is 1 MHz to 166 MHz (commercial) or 1 MHz to 150 MHz (industrial) with a 40% to 60% duty cycle."
      },
      {
        "number": "5",
        "name": "XTALOUT",
        "type": "output",
        "description": "Reference crystal feedback; for a driven clock input, XTALOUT must be left floating."
      },
      {
        "number": "6",
        "name": "XBUF",
        "type": "output",
        "description": "Buffered reference clock output, which is simply the buffered reference."
      },
      {
        "number": "7",
        "name": "CLKD",
        "type": "output",
        "description": "Configurable clock output D; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "8",
        "name": "CLKE",
        "type": "output",
        "description": "Configurable clock output E; it is sourced from PLL1 through a post divider programmable to /2, /3, or /4, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "9",
        "name": "CLKB",
        "type": "output",
        "description": "Configurable clock output B; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "10",
        "name": "CLKA",
        "type": "output",
        "description": "Configurable clock output A; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Ground; all grounds must be connected to the same ground plane."
      },
      {
        "number": "12",
        "name": "S0",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 0, used with S1 and S2 to select among eight programmed frequency settings."
      },
      {
        "number": "13",
        "name": "S1",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 1, used with S0 and S2 to select among eight programmed frequency settings."
      },
      {
        "number": "14",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and the maximum DC input voltage is limited to AVDD + 0.5 V."
      },
      {
        "number": "15",
        "name": "S2/SUSPEND",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 2; optionally a suspend mode control input that shuts off a configured set of outputs and/or PLLs when LOW."
      },
      {
        "number": "16",
        "name": "SHUTDOWN/OE",
        "type": "input",
        "description": "Places outputs in three-state and shuts down the chip when Low; optionally, it only tristates the outputs without shutting down the chip, and the three-state timing is 300 ns maximum."
      }
    ],
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      "Manufacturer": "Infineon Cypress Semicon",
      "Package": "TSSOP-16",
      "Category": "Clock/Timing",
      "Pins": "16"
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