CY22392FXIT

{
  "slug": "cy22392fxit",
  "version": "0.1.0",
  "type": "component",
  "description": "Infineon Cypress Semicon Clock Generators, PLLs, Frequency Synthesizers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "clock-timing",
    "cy22392fxit",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cy22392fxit.kicad_sym",
    "cy22392fxit.kicad_mod",
    "cy22392fxit.glb",
    "cy22392fxit.step",
    "cy22392fxit.lbr",
    "docs/hero.png",
    "docs/cy22392fxit-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cy22392fxit-hero.glb",
    "cy22392fxit-hero.overlay.json",
    "cy22392fxit-etched.glb"
  ],
  "component": {
    "mpn": "CY22392FXIT",
    "manufacturer": "Infineon Cypress Semicon",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Clock/Timing",
    "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120392822784",
    "parts": {
      "symbol": "cy22392fxit.kicad_sym",
      "footprint": "cy22392fxit.kicad_mod",
      "model_3d": "cy22392fxit-hero.glb",
      "model_3d_plain": "cy22392fxit-etched.glb",
      "model_3d_step": "cy22392fxit-etched.step",
      "model_3d_step_plain": "cy22392fxit.step",
      "lbr": "cy22392fxit.lbr"
    },
    "distributor_links": {
      "lcsc": "C2759946",
      "digikey": "448-CY22392FXITTR-ND",
      "mouser": "727-CY22392FXIT"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T23:18:46Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "448-CY22392FXITTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "727-CY22392FXIT",
        "status": "found",
        "lifecycle": "Not Recommended for New Designs"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CLKC",
        "type": "output",
        "description": "Configurable clock output C; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "2",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and all VDD pins must reach the specified voltage with monotonic ramps."
      },
      {
        "number": "3",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground; all grounds must be connected to the same ground plane."
      },
      {
        "number": "4",
        "name": "XTALIN",
        "type": "input",
        "description": "Reference crystal input or external reference clock input; crystal range is 8 MHz to 30 MHz, and an external reference clock is 1 MHz to 166 MHz (commercial) or 1 MHz to 150 MHz (industrial) with a 40% to 60% duty cycle."
      },
      {
        "number": "5",
        "name": "XTALOUT",
        "type": "output",
        "description": "Reference crystal feedback; for a driven clock input, XTALOUT must be left floating."
      },
      {
        "number": "6",
        "name": "XBUF",
        "type": "output",
        "description": "Buffered reference clock output, which is simply the buffered reference."
      },
      {
        "number": "7",
        "name": "CLKD",
        "type": "output",
        "description": "Configurable clock output D; its output comes from the crosspoint switch through a programmable 7-bit post divider, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "8",
        "name": "CLKE",
        "type": "output",
        "description": "Configurable clock output E; it is sourced from PLL1 through a post divider programmable to /2, /3, or /4, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "9",
        "name": "CLKB",
        "type": "output",
        "description": "Configurable clock output B; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "10",
        "name": "CLKA",
        "type": "output",
        "description": "Configurable clock output A; its 7-bit post divider selects one of two programmable registers based on the S0, S1, S2 combination, and the outputs are designed to drive a single-point load of 15 pF total lumped capacitance."
      },
      {
        "number": "11",
        "name": "GND",
        "type": "power_in",
        "description": "Ground; all grounds must be connected to the same ground plane."
      },
      {
        "number": "12",
        "name": "S0",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 0, used with S1 and S2 to select among eight programmed frequency settings."
      },
      {
        "number": "13",
        "name": "S1",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 1, used with S0 and S2 to select among eight programmed frequency settings."
      },
      {
        "number": "14",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog power supply; VDD/AVDD must be within 3.135 V to 3.465 V (3.3 V nominal), and the maximum DC input voltage is limited to AVDD + 0.5 V."
      },
      {
        "number": "15",
        "name": "S2/SUSPEND",
        "type": "input",
        "description": "General Purpose Input for frequency control, bit 2; optionally a suspend mode control input that shuts off a configured set of outputs and/or PLLs when LOW."
      },
      {
        "number": "16",
        "name": "SHUTDOWN/OE",
        "type": "input",
        "description": "Places outputs in three-state and shuts down the chip when Low; optionally, it only tristates the outputs without shutting down the chip, and the three-state timing is 300 ns maximum."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The Figure 1 pin-layout drawing is garbled in the extracted text, so the physical placement of pins ; The datasheet does not state pin electrical types. Types were assigned by function: XTALOUT as outpu; The datasheet's Figure 1 caption covers both the 16-pin TSSOP and 16-pin SOIC packages with one pino"
        ],
        "pages_sent": 14,
        "cost_usd": 0.0172,
        "at": "2026-10-20T23:13:32"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588904120392822784",
        "pages": 14,
        "sha256": "0cac945e21946252",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cy22392fxit-etched.step",
        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "a9ca009f65b6f977e4143d20e8072bd9bd4e40a54296dec6631ad2ddd1e56d85",
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        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
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  }
}