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CY22150FZXCT

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Cypress Semicon Clock Generators / Frequency Synthesizers / PLL, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY22150FZXCT

Cypress Semicon · Clock Generators / Frequency Synthesizers / PLL · TSSOP-16

CY22150FZXCT from Cypress Semicon, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XIN input Reference input driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz), with programmable input load capacitors.
2 VDD power_in 3.3 V voltage supply.
3 AVDD power_in 3.3 V analog voltage supply.
4 SDA bidirectional I2C serial data input/output.
5 AVSS power_in Analog ground.
6 VSSL power_in LCLK ground.
7 LCLK1 output Configurable clock output 1 at VDDL level (3.3 V or 2.5 V).
8 LCLK2 output Configurable clock output 2 at VDDL level (3.3 V or 2.5 V).
9 LCLK3 output Configurable clock output 3 at VDDL level (3.3 V or 2.5 V).
10 SCL input I2C serial clock input.
11 VDDL power_in LCLK voltage supply (2.5 V or 3.3 V).
12 LCLK4 output Configurable clock output 4 at VDDL level (3.3 V or 2.5 V).
13 VSS power_in Ground.
14 CLK5 output Configurable clock output 5 (3.3 V).
15 CLK6 output Configurable clock output 6 (3.3 V).
16 XOUT output Reference output; float XOUT if XIN is driven by an external clock source.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TSSOP-16
Category Clock and Timing
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD -0.5 7 V 14
I/O Supply Voltage VDDL -0.5 7 V 14
Storage Temperature TS -65 125 °C Rated for 10 years 14
Junction Temperature TJ 125 °C 14
Package Power Dissipation, Commercial Temperature 450 mW 14
Digital Inputs -0.3 V AVSS, 0.3 to AVDD + 0.3 V 14
ESD Static Discharge Voltage 2000 V per MIL-STD-833, Method 3015 14
Operating Voltage VDD 3.135 3.3 3.465 V 14
Operating Voltage (VDDL 3.3 V) VDDLHI 3.135 3.3 3.465 V 14
Operating Voltage (VDDL 2.5 V) VDDLLO 2.375 2.5 2.625 V 14
Ambient Commercial Temp TAC 0 70 °C 14
Max. Load Capacitance CLOAD 15 pF VDD/VDDL = 3.3 V 14
Driven REF fREFD 1 133 MHz 14
Crystal REF fREFC 8 30 MHz 14
Power up time tPU 0.05 500 ms power ramps must be monotonic 14
Output High Current IOH3.3 12 24 mA VOH = VDD, 0.5 V, VDD/VDDL = 3.3 V (sink) 15
Output Low Current IOL3.3 12 24 mA VOL = 0.5 V, VDD/VDDL = 3.3 V (source) 15
Output High Current IOH2.5 8 16 mA VOH = VDDL, 0.5 V, VDDL = 2.5 V (source) 15
Output Low Current IOL2.5 8 16 mA VOL = 0.5, VDDL = 2.5 V (sink) 15
Input High Voltage VIH 0.7 VDD CMOS levels, 70% of VDD 15
Input Low Voltage VIL 0.3 VDD CMOS levels, 30% of VDD 15
Input Capacitance CIN 7 pF SCL and SDA Pins 15
Hysteresis of Schmitt triggered inputs VHYS 0.05 VDD SCL and SDA Pins 15
Output Frequency, Commercial t1 0.08 200 MHz Clock output limit, 3.3 V 16
Output Frequency, Commercial t1 0.08 166.6 MHz Clock output limit, 2.5 V 16
Output Duty Cycle t2LO 45 50 55 % t1/t2, fOUT < 166 MHz, 50% of VDD 16
Output Duty Cycle t2HI 40 50 60 % t1/t2, fOUT > 166 MHz, 50% of VDD 16
Rising Edge Slew Rate (VDDL = 2.5 V) t3LO 0.6 1.2 V/ns 20% to 80% of VDDL 16
Falling Edge Slew Rate (VDDL = 2.5 V) t4LO 0.6 1.2 V/ns 80% to 20% of VDDL 16
Rising Edge Slew Rate (VDDL = 3.3 V) t3HI 0.8 1.4 V/ns 20% to 80% of VDD/VDDL 16
Falling Edge Slew Rate (VDDL = 3.3 V) t4HI 0.8 1.4 V/ns 80% to 20% of VDD/VDDL 16
Output-output Skew t5 250 ps between related outputs 16
PLL Lock Time t10 0.3 3 ms 16
Input Leakage Current IIZ 5 µA SCL and SDA Pins 15
Supply Current AVDD/VDD IVDD 45 mA AVDD/VDD Current 15
Supply Current VDDL IVDDL3.3 25 mA VDDL = 3.465 V 15
Supply Current VDDL IVDDL2.5 17 mA VDDL = 2.625 V 15
Peak-to-peak period jitter t6 250 ps Peak-to-peak period jitter 16
Theta JA θJA 115 °C/W 15

CAD (KiCad official)

  • Symbol: CY22150FZXCT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cy22150fzxct-etched.step / cy22150fzxct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy22150fzxct.step / cy22150fzxct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (24 pp, sha256 8adebbf97d2d391a, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF