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CY15B102QN-50SXE

Public Made by Adom

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Cypress Semicon Pre-ordered Products, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy15b102qn-50sxefactory-2.0.0extractor-text

Verified CY15B102QN-50SXE

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY15B102QN-50SXE · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C2953691, digikey 448-CY15B102QN-50SXE-ND, mouser 727-CY15B102QN-50SXE
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pauf9ns4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy15b102qn-50sxe.kicad_sym✓ cy15b102qn-50sxe.kicad_mod✓ cy15b102qn-50sxe.step
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CY15B102QN-50SXE

Cypress Semicon · Pre-ordered Products · SOIC-8

CY15B102QN-50SXE from Cypress Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active LOW chip select that activates the device; when HIGH the device enters low-power standby, ignores other inputs and tristates the output, and a falling edge on CS must occur before every opcode.
2 SO output Serial data output, driven during a read and tristated at all other times, with data transitions on the falling edge of SCK.
3 WP input Active LOW write protect that prevents writes to the status register when the WPEN bit is set to 1; must be tied to VDD if not used.
4 VSS power_in Ground for the device, must be connected to the system ground.
5 SI input Serial data input sampled on the rising edge of SCK and ignored at other times; must always be driven to a valid logic level to meet IDD specifications, and may be connected to SO for a single-pin data interface.
6 SCK input Serial clock that synchronizes all I/O activity, latching inputs on the rising edge with outputs on the falling edge, at any frequency from 0 to 50 MHz.
7 DNU passive Do not use; leave floating (not connected on the board) or tie to VDD.
8 VDD power_in Power supply input to the device (1.8 V to 3.6 V for CY15B102QN).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SOIC-8
Category Electronic Tools/Instruments/Consumables
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VDD 1.8 3.3 3.6 V CY15B102QN 25
Ambient temperature (Automotive-E) TA -40 125 °C Operating range 24
Storage temperature -65 150 °C 23
Maximum junction temperature 135 °C 23
Supply voltage on VDD relative to VSS VDD -0.5 4.1 V CY15B102QN 23
Package power dissipation capability 1 W TA = 25°C 23
Surface mount lead soldering temperature 260 °C 3 seconds 23
DC output current 15 mA 1 output at a time, 1s duration 23
ESD voltage, Human Body Model 2 kV JESD22-A114-B 23
ESD voltage, Charged Device Model 500 V JESD22-C101-A 23
VDD supply current IDD 0.5 1.4 mA VDD = 1.8 V to 3.6 V; fSCK = 1 MHz; SO = Open 25
VDD supply current IDD 4.3 8 mA VDD = 1.8 V to 3.6 V; fSCK = 40 MHz; SO = Open 25
VDD supply current IDD 6 8 mA VDD = 1.8 V to 3.6 V; fSCK = 50 MHz; SO = Open 25
VDD standby current ISB 3.2 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 25°C 25
VDD standby current ISB 75 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 85°C 25
VDD standby current ISB 350 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 125°C 25
Deep power-down current IDPD 1.3 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 25°C 25
Deep power-down current IDPD 17 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 85°C 25
Deep power-down current IDPD 80 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 125°C 25
Hibernate mode current IHBN 0.1 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 25°C 25
Hibernate mode current IHBN 1.6 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 85°C 25
Hibernate mode current IHBN 14 µA VDD = 1.8 V to 3.6 V; CS = VDD; TA = 125°C 25
Input leakage current on I/O pins except WP pin ILI -5 5 µA VSS < VIN < VDD 25
Input leakage current on WP pin ILI -100 5 µA VSS < VIN < VDD 25
Output leakage current ILO -5 5 µA VSS < VOUT < VDD 26
Input LOW voltage VIL -0.3 V max is 0.3 × VDD as printed 26
Output HIGH voltage VOH1 2.4 V IOH = -1 mA, VDD = 2.7 V 26
Output LOW voltage VOL1 0.4 V IOL = 2 mA, VDD = 2.7 V 26
Output LOW voltage VOL2 0.2 V IOL = 150 µA 26
Data retention TDR 11000 Hours TA = 125°C 27
Data retention TDR 11 Years TA = 105°C 27
Data retention TDR 121 Years TA = 85°C 27
SCK clock frequency fSCK 0 50 MHz 50 MHz column 32
Clock HIGH time tCH 9 ns 50 MHz column 32
Clock LOW time tCL 9 ns 50 MHz column 32
Chip select setup tCSS 5 ns 50 MHz column 32
Chip select hold - SPI mode 0 tCSH 5 ns 50 MHz column 32
Chip select hold - SPI mode 3 tCSH1 10 ns 50 MHz column 32
Output disable time tHZCS 10 ns 50 MHz column 32
Output data valid time tCO 8 ns 50 MHz column 32
Output hold time tOH 1 ns 50 MHz column 32
Deselect time tCS 40 ns 50 MHz column 32
Data setup time tSD 5 ns 50 MHz column 32
Data hold time tHD 5 ns 50 MHz column 32
WP setup time (w.r.t CS) tWPS 20 ns 50 MHz column 32
WP hold time (w.r.t CS) tWPH 20 ns 50 MHz column 32
Power-up VDD(min) to first access (CS LOW) tPU 450 µs 34
VDD power-up ramp rate tVR 30 µs/V 34
VDD power-down ramp rate tVF 20 µs/V 34
CS HIGH to enter deep power-down tENTDPD 3 µs 34
Recovery time from deep power-down mode tEXTDPD 10 µs CS LOW to ready for access 34
CS HIGH to enter hibernate tENTHIB 3 µs 34
Recovery time from hibernate mode tEXTHIB 450 µs CS LOW to ready for access 34
Low VDD where initialization must occur VDD(low) 0.6 V 34

CAD (KiCad official)

  • Symbol: CY15B102QN-50SXE
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cy15b102qn-50sxe-etched.step / cy15b102qn-50sxe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy15b102qn-50sxe.step / cy15b102qn-50sxe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (44 pp, sha256 9412812a28df342f, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF