CW32L083VCT6 from CW, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PE02	bidirectional	TTa I/O, high-impedance input after reset; alternates LPTIM_ETR, LVD_OUT, IR_OUT, GTIM1_ETR, ATIM_BK; analog SEG49.
2	PE03	bidirectional	TTa I/O, high-impedance input after reset; alternates LPTIM_CH1, UART5_RXD, I2C2_SCL, SPI1_CS, GTIM1_CH4, ATIM_CH1B; analog SEG48.
3	PE04	bidirectional	TC I/O, high-impedance input after reset; alternates LPTIM_CH2, UART5_TXD, I2C2_SDA, SPI1_SCK, GTIM1_CH3, ATIM_CH2B.
4	PE05	bidirectional	TC I/O, high-impedance input after reset; alternates UART5_CTS, UART6_RXD, SPI1_MISO, GTIM1_CH2, ATIM_CH3B.
5	PE06	bidirectional	TC I/O, high-impedance input after reset; alternates UART5_RTS, UART6_TXD, SPI1_MOSI, GTIM1_CH1, ATIM_ETR.
6	Vcore	power_out	Internal core-logic supply node from the on-chip regulator; decouple per the power-system note (Figure 7-3).
7	PC13	bidirectional	TC I/O, high-impedance input after reset; alternates PLL_OUT, RTC_1Hz, UART1_CTS, RTC_OUT, BTIM_ETR, GTIM3_ETR, RTC_TAMP.
8	PC14-OSC32_IN	bidirectional	TC I/O with LSE oscillator input (OSC32_IN) function; alternates AUTOTRIM_ETR, GTIM4_CH4, UART1_RTS, UART4_TXD, SPI2_MISO, GTIM3_TOGP, GTIM3_CH1.
9	PC15-OSC32_OUT	bidirectional	TC I/O with LSE oscillator output (OSC32_OUT) function; alternates HSE_OUT, GTIM4_CH3, GTIM4_ETR, UART4_RXD, SPI2_MOSI, GTIM3_TOGN, GTIM3_CH2.
10	PF09	bidirectional	TC I/O, high-impedance input after reset; alternates UART2_TXD, UART3_RXD, BTIM3_TOGP, RTC_OUT, GTIM1_CH1, HCLK_OUT.
11	PF10	bidirectional	TC I/O, high-impedance input after reset; alternates UART2_RXD, UART3_TXD, BTIM3_TOGN, HSIOSC_OUT, GTIM1_CH2, MCO_OUT.
12	PF00-OSC_IN	bidirectional	TC I/O with HSE oscillator input (OSC_IN) function; alternates AUTOTRIM_ETR, GTIM4_CH2, I2C1_SDA, BTIM1_TOGN, SPI2_SCK, GTIM2_TOGP, GTIM3_CH3.
13	PF01-OSC_OUT	bidirectional	TC I/O with HSE oscillator output (OSC_OUT) function; alternates LSE_OUT, GTIM4_CH1, I2C1_SCL, BTIM1_TOGP, SPI2_CS, GTIM2_TOGN, GTIM3_CH4.
14	NRST	input	Chip reset input with internal pull-up of 7-9 kOhm; minimum reset pulse width 20 us.
15	PC00	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_CTS, GTIM2_CH4, SPI1_CS, LPTIM_CH1, UART5_RXD, ATIM_CH1A, I2C2_SCL; analog SEG23.
16	PC01	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RTS, GTIM2_CH3, SPI1_SCK, LPTIM_OUT, UART5_TXD, ATIM_CH2A, I2C2_SDA; analog SEG22.
17	PC02	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RXD, GTIM2_CH2, SPI1_MISO, LPTIM_CH2, UART1_TXD, ATIM_CH3A; analog SEG21.
18	PC03	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_TXD, GTIM2_CH1, SPI1_MOSI, LPTIM_ETR, UART1_RXD, ATIM_BK; analog SEG20.
19	PF02	bidirectional	TC I/O, high-impedance input after reset; alternates UART5_CTS, LVD_OUT, LSI_OUT, GTIM3_TOGP, MCO_OUT.
20	VSSA	power_in	Analog ground.
21	VDDA	power_in	Analog supply for ADC, reset circuit, RC oscillator and PLL, 1.65 V to 5.5 V; must be greater than or equal to VDD.
22	PF08	bidirectional	TC I/O, high-impedance input after reset; alternates UART5_RTS, PLL_OUT, PCLK_OUT, GTIM3_TOGN.
23	PA00	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_CTS, UART6_CTS, RTC_TAMP, VC1_OUT, SPI2_MISO, GTIM2_CH1, GTIM2_ETR; analog ADC_AIN0, VC1_CH0, LVD_CH1.
24	PA01	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RTS, UART6_RTS, I2C2_SCL, LVD_OUT, SPI2_MOSI, GTIM2_CH2, RTC_TAMP; analog ADC_AIN1, VC1_CH1, SEG19.
25	PA02	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_TXD, UART6_TXD, I2C2_SDA, VC2_OUT, SPI2_SCK, GTIM2_CH3, AUTOTRIM_ETR; analog ADC_AIN2, VC1_CH2, SEG18.
26	PA03	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RXD, UART6_RXD, GTIM2_CH2, PCLK_OUT, SPI2_CS, GTIM2_CH4, ATIM_CH3A; analog ADC_AIN3, VC1_CH3, SEG17.
27	VSS	power_in	Digital ground.
28	VDD	power_in	Digital supply for I/O and internal regulator, 1.65 V to 5.5 V.
29	PA04	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_TXD, UART2_CTS, I2C2_SCL, HCLK_OUT, SPI1_CS, GTIM2_ETR, ATIM_CH2A; analog ADC_AIN4, VC1_CH4.
30	PA05	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_ETR, UART2_RTS, I2C2_SDA, BTIM2_TOGN, SPI1_SCK, GTIM2_CH1, ATIM_CH1A; analog ADC_AIN5, VC1_CH5.
31	PA06	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM3_CH1, UART2_TXD, VC1_OUT, BTIM2_TOGP, SPI1_MISO, GTIM1_CH1, ATIM_BK; analog ADC_AIN6, VC1_CH6, SEG16.
32	PA07	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM4_CH1, UART2_RXD, VC2_OUT, BTIM1_TOGN, SPI1_MOSI, GTIM1_CH2, ATIM_CH1B; analog ADC_AIN7, VC1_CH7, SEG15.
33	PC04	bidirectional	TTa I/O, high-impedance input after reset; alternates UART1_TXD, UART6_RXD, IR_OUT, LSI_OUT; analog ADC_AIN8, SEG14.
34	PC05	bidirectional	TTa I/O, high-impedance input after reset; alternates UART1_RXD, UART6_TXD, MCO_OUT, LPTIM_ETR, LPTIM_OUT; analog ADC_AIN9, SEG13.
35	PB00	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_RXD, UART1_CTS, I2C2_SCL, BTIM1_TOGP, HSIOSC_OUT, GTIM1_CH3, ATIM_CH2B; analog ADC_AIN10/ExRef, VC2_CH0, LVD_CH2, SEG12.
36	PB01	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_TXD, UART1_RTS, I2C2_SDA, GTIM4_TOGP, BTIM3_TOGN, GTIM1_CH4, ATIM_CH3B; analog ADC_AIN11, VC2_CH1, SEG11.
37	PB02	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_CTS, UART1_TXD, LPTIM_OUT, GTIM4_TOGN, BTIM3_TOGP, GTIM1_ETR, ATIM_CH1A; analog ADC_AIN12, VC2_CH2.
38	PE07	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_RTS, LPTIM_CH1, GTIM1_CH4, GTIM4_ETR, BTIM_ETR, ATIM_CH2A; analog SEG47.
39	PE08	bidirectional	TTa I/O, high-impedance input after reset; alternates UART1_TXD, LPTIM_CH2, GTIM1_CH3, SPI1_CS, GTIM4_CH1, ATIM_CH3A; analog SEG46.
40	PE09	bidirectional	TTa I/O, high-impedance input after reset; alternates UART1_RXD, LPTIM_OUT, GTIM1_ETR, SPI1_SCK, GTIM3_CH1, ATIM_BK; analog SEG45.
41	PE10	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_TXD, LPTIM_ETR, GTIM1_CH2, SPI1_MISO, GTIM3_CH2, ATIM_ETR; analog SEG44.
42	PE11	bidirectional	TC I/O, high-impedance input after reset; alternates UART4_RXD, UART1_RXD, GTIM1_CH1, SPI1_MOSI, GTIM3_CH3.
43	PE12	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_TXD, GTIM2_CH4, SPI2_CS, GTIM3_CH4, ATIM_CH1B; analog SEG43.
44	PE13	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RXD, GTIM2_CH3, SPI2_SCK, GTIM4_CH2, ATIM_CH2B; analog SEG42.
45	PE14	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_TXD, GTIM2_CH2, SPI2_MISO, GTIM4_CH3, ATIM_CH3B; analog SEG41.
46	PE15	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_RXD, GTIM2_CH1, SPI2_MOSI, GTIM4_CH4, ATIM_BK; analog SEG40.
47	PB10	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_RTS, UART4_RXD, I2C1_SCL, I2C2_SCL, SPI2_SCK, GTIM2_CH3, ATIM_CH2A; analog VC2_CH3, SEG10.
48	PB11	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM4_ETR, UART4_TXD, I2C1_SDA, I2C2_SDA, BTIM_ETR, GTIM2_CH4, ATIM_CH3A; analog LVD_CH3, SEG9.
49	VSS	power_in	Digital ground.
50	VDD	power_in	Digital supply for I/O and internal regulator, 1.65 V to 5.5 V.
51	PB12	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_TOGP, GTIM4_CH4, LSE_OUT, SPI2_CS, SPI1_CS, GTIM1_TOGP, ATIM_BK; analog SEG8.
52	PB13	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_TOGN, GTIM4_CH3, I2C2_SCL, SPI2_SCK, SPI1_SCK, GTIM1_TOGN, ATIM_CH1B; analog SEG7.
53	PB14	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_CH1, GTIM4_CH2, I2C2_SDA, SPI2_MISO, SPI1_MISO, RTC_OUT, ATIM_CH2B; analog SEG6.
54	PB15	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_CH2, GTIM4_CH1, BTIM2_TOGN, SPI2_MOSI, SPI1_MOSI, RTC_1Hz, ATIM_CH3B; analog SEG5.
55	PD08	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_CH3, LPTIM_OUT, UART1_TXD, SPI2_CS, GTIM1_CH1, ATIM_CH1A; analog SEG39.
56	PD09	bidirectional	TTa I/O, high-impedance input after reset; alternates GTIM2_CH4, LPTIM_CH2, UART1_RXD, SPI2_SCK, GTIM1_CH2, ATIM_CH2A; analog SEG38.
57	PD10	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_TXD, LPTIM_CH1, GTIM4_CH1, SPI2_MISO, GTIM1_CH3, ATIM_CH3A; analog SEG37.
58	PD11	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_RXD, LPTIM_ETR, GTIM4_CH2, SPI2_MOSI, GTIM1_CH4, ATIM_BK; analog SEG36.
59	PD12	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_CTS, UART4_RXD, GTIM4_CH3, SPI1_CS, BTIM3_TOGP, AUTOTRIM_ETR; analog SEG35.
60	PD13	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_RTS, UART4_TXD, GTIM4_CH4, SPI1_SCK, BTIM3_TOGN; analog SEG34.
61	PD14	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_TXD, HCLK_OUT, GTIM2_ETR, SPI1_MISO; analog SEG33.
62	PD15	bidirectional	TTa I/O, high-impedance input after reset; alternates UART2_RXD, PCLK_OUT, BTIM_ETR, SPI1_MOSI; analog SEG32.
63	PC06	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RXD, UART3_TXD, BTIM2_TOGP, GTIM2_CH4, ATIM_CH1B; analog SEG4.
64	PC07	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_TXD, UART3_RXD, BTIM2_TOGN, GTIM2_CH3, ATIM_CH2B; analog SEG3.
65	PC08	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_CTS, UART6_TXD, GTIM4_ETR, GTIM2_CH2, ATIM_CH3B; analog SEG2.
66	PC09	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RTS, UART6_RXD, I2C1_SDA, GTIM2_CH1, ATIM_ETR; analog SEG1.
67	PA08	bidirectional	TTa I/O, high-impedance input after reset; alternates LPTIM_ETR, UART1_TXD, BTIM2_TOGP, MCO_OUT, LVD_OUT, GTIM3_ETR, ATIM_CH1A; analog VC2_CH4, SEG0.
68	PA09	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_TXD, UART1_RXD, I2C1_SCL, BTIM1_TOGN, SPI1_CS, GTIM3_CH1, ATIM_CH2A; analog VC2_CH5, COM0.
69	PA10	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RXD, UART1_CTS, I2C1_SDA, BTIM1_TOGP, SPI1_SCK, GTIM3_CH2, ATIM_CH3A; analog VC2_CH6, COM1.
70	PA11	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_CTS, UART1_RTS, I2C2_SCL, VC1_OUT, SPI1_MISO, GTIM3_CH3; analog VC2_CH7, COM2.
71	PA12	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RTS, BTIM_ETR, I2C2_SDA, VC2_OUT, SPI1_MOSI, GTIM3_CH4, ATIM_ETR; analog COM3.
72	PA13/SWDIO	bidirectional	TC I/O configured as SWDIO after reset with internal pull-up enabled; alternates I2C1_SDA, UART1_RXD, UART2_TXD, I2C2_SCL, IR_OUT.
73	PF06	bidirectional	TC I/O, high-impedance input after reset; alternates UART6_CTS, I2C1_SCL, GTIM4_TOGP, UART2_CTS, I2C2_SCL, GTIM3_TOGP, BTIM3_TOGN.
74	VSS	power_in	Digital ground.
75	VDD	power_in	Digital supply for I/O and internal regulator, 1.65 V to 5.5 V.
76	PA14/SWCLK	input	TC pin configured as SWCLK after reset with internal pull-up enabled; alternates UART3_TXD, I2C1_SCL, UART1_TXD, UART2_RXD, I2C2_SDA.
77	PA15	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_TXD, SPI1_CS, GTIM2_ETR, ATIM_CH1B; analog SEG55.
78	PC10	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_TXD, GTIM3_CH1, HCLK_OUT, BTIM1_TOGP, VC1_OUT, LPTIM_CH1, ATIM_CH2B; analog SEG31/COM4.
79	PC11	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RXD, GTIM3_CH2, IR_OUT, BTIM1_TOGN, VC2_OUT, LPTIM_CH2, ATIM_CH3B; analog SEG30/COM5.
80	PC12	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_TXD, PCLK_OUT, LVD_OUT, UART6_RXD, PLL_OUT, HSIOSC_OUT; analog SEG29/COM6.
81	PD00	bidirectional	TC I/O, high-impedance input after reset; alternates UART6_RXD, I2C2_SCL, AUTOTRIM_ETR, SPI2_CS, MCO_OUT.
82	PD01	bidirectional	TC I/O, high-impedance input after reset; alternates UART6_TXD, I2C2_SDA, RTC_1Hz, SPI2_SCK, RTC_TAMP.
83	PD02	bidirectional	TTa I/O, high-impedance input after reset; alternates UART5_RXD, GTIM4_CH1, BTIM_ETR, UART6_TXD, RTC_1Hz, GTIM3_ETR, ATIM_ETR; analog SEG28/COM7.
84	PD03	bidirectional	TTa I/O, high-impedance input after reset; alternates UART6_CTS, I2C2_SCL, VC1_OUT, SPI2_MISO, GTIM1_CH3, ATIM_BK; analog SEG54.
85	PD04	bidirectional	TC I/O, high-impedance input after reset; alternates UART6_RTS, I2C2_SDA, VC2_OUT, SPI2_MOSI, GTIM1_CH4, ATIM_CH3A.
86	PD05	bidirectional	TC I/O, high-impedance input after reset; alternates UART4_TXD, GTIM2_CH1, UART3_TXD, LPTIM_CH1, BTIM2_TOGP, LSI_OUT, ATIM_CH2A.
87	PD06	bidirectional	TC I/O, high-impedance input after reset; alternates I2C1_SCL, GTIM2_CH4, UART3_RXD, LPTIM_CH2, BTIM2_TOGN, GTIM2_TOGP, ATIM_CH1A.
88	PD07	bidirectional	TC I/O, high-impedance input after reset; alternates I2C1_SDA, GTIM2_CH3, MCO_OUT, UART2_RXD, SPI1_CS, GTIM2_TOGN, ATIM_CH1B.
89	PB03	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_RTS, GTIM2_CH2, UART4_CTS, UART2_TXD, SPI1_SCK, GTIM1_ETR, ATIM_CH2B; analog SEG27/VLCD4.
90	PB04	bidirectional	TTa I/O, high-impedance input after reset; alternates UART3_CTS, GTIM4_ETR, UART4_RTS, UART2_RXD, SPI1_MISO, GTIM1_CH1, ATIM_CH3B; analog SEG26/VLCD3.
91	PB05	bidirectional	TTa I/O, high-impedance input after reset; alternates UART4_RXD, GTIM3_CH4, LPTIM_CH1, UART2_RTS, SPI1_MOSI, GTIM1_CH2, ATIM_CH1A; analog SEG25/VLCD2.
92	PB06	bidirectional	TTa I/O, high-impedance input after reset; alternates UART6_TXD, GTIM3_CH3, LPTIM_ETR, I2C1_SCL, SPI2_MOSI, GTIM1_TOGP, ATIM_CH2A; analog SEG24/VLCD1.
93	PB07	bidirectional	TTa I/O, high-impedance input after reset; alternates UART6_RXD, GTIM3_CH2, LPTIM_CH2, I2C1_SDA, SPI2_MISO, GTIM1_TOGN, ATIM_CH3A.
94	PF03/BOOT	input	Dedicated BOOT pin that selects between the internal bootloader and user program at startup.
95	PB08	bidirectional	TTa I/O, high-impedance input after reset; alternates I2C1_SCL, GTIM3_CH1, UART5_TXD, GTIM4_CH2, SPI2_SCK, GTIM1_CH3, ATIM_ETR; analog SEG53.
96	PB09	bidirectional	TTa I/O, high-impedance input after reset; alternates I2C1_SDA, GTIM4_CH1, UART5_RXD, IR_OUT, SPI2_CS, GTIM1_CH4, ATIM_BK; analog SEG52.
97	PE00	bidirectional	TTa I/O, high-impedance input after reset; alternates I2C2_SCL, GTIM4_CH2, LPTIM_ETR, PCLK_OUT, GTIM2_TOGP, GTIM1_CH1, GTIM4_TOGP; analog SEG51.
98	PE01	bidirectional	TTa I/O, high-impedance input after reset; alternates I2C2_SDA, GTIM4_CH3, LPTIM_OUT, HCLK_OUT, GTIM2_TOGN, GTIM1_CH2, GTIM4_TOGN; analog SEG50.
99	VSS	power_in	Digital ground.
100	VDD	power_in	Digital supply for I/O and internal regulator, 1.65 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	CW
Package	LQFP-100(14x14)
Category	Single Chip Microcomputer/Microcontroller
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD-VSS external main supply voltage	VDD - VSS	-0.3		6	V		45
VDDA-VSS external analog supply voltage	VDDA-VSS	-0.3		6	V		45
Maximum allowed difference VDD above VDDA	VDD-VDDA			0.3	V	VDD greater than VDDA	45
Maximum difference between VDD pins	/ΔVDDx/			0.05	V		45
Maximum difference between VSS pins	/VSSX-VSS/			0.05	V		45
Total VDD supply line sink current sum	ΣIVDD			120	mA		45
Total VSS supply line source current sum	ΣIVSS			-120	mA		45
Single VDD supply line sink current	IVDD(PIN)			100	mA		45
Single VSS supply line source current	IVSS(PIN)			-100	mA		45
Single I/O or control pin sink current	IIO(PIN)			25	mA		45
Single I/O or control pin source current	IIO(PIN)			-25	mA		45
Total I/O pins sink current sum	ΣIIO(PIN)			80	mA		45
Total I/O pins source current sum	ΣIIO(PIN)			-80	mA		45
Injection current on TC and RST pins	IINJ(PIN)	-5		5	mA		45
Injection current on TTa pins	IINJ(PIN)	-5		5	mA		45
Total injection current all I/O pins	ΣIINJ(PIN)	-25		25	mA		45
Storage temperature range	TSTG	-65		150	℃		45
Maximum junction temperature	TJ			105	℃		45
Internal AHB bus frequency	fHCLK	0		64	MHz	VDD ≥ 1.8V	46
Internal APB bus frequency	fPCLK	0		64	MHz	VDD ≥ 1.8V	46
Internal AHB bus frequency	fHCLK	0		24	MHz	1.65V ≤ VDD < 1.8V	46
Internal APB bus frequency	fPCLK	0		24	MHz	1.65V ≤ VDD < 1.8V	46
Standard operating voltage	VDD	1.65		5.5	V		46
Analog operating voltage	VDDA	1.65		5.5	V	must equal VDD	46
Power dissipation LQFP100	PD			488	mW	TA=85℃	46
Power dissipation LQFP64 (reference row)	PD			435	mW	TA=85℃	46
Ambient temperature (temperature grade 6)	TA	-40		85	℃	maximum power dissipation	46
Ambient temperature (temperature grade 6)	TA	-40		105	℃	low power dissipation	46
Junction temperature range	TJ	-40		105	℃	temperature grade 6	46
POR/BOR power-on/power-down reset threshold falling edge	VPOR/BOR	1.45	1.5	1.55	V		47
POR/BOR power-on/power-down reset threshold rising edge	VPOR/BOR	1.5	1.55	1.6	V		47
BOR hysteresis	VBORhyst			50	mV		47
Reset duration	tRSTTEMPO	4	6.5	13	ms		47
Internal 1.5V reference voltage	VREFINT1V5	1.485	1.5	1.515	V	-40℃ < TA < +85℃	47
Internal 2.5V reference voltage	VREFINT2V5	2.475	2.5	2.525	V	-40℃ < TA < +85℃	47
Internal reference voltage distribution over full temperature range	ΔVREFINT			10	mV	VDDA = 3V	47
Internal reference temperature coefficient	TCoeff	-60	1	60	ppm/℃		47
Run mode supply current, code from FLASH, 64MHz	IDD		13.6	15	mA	VDD=VDDA=5.5V, HSI or HSE, PLL on, all peripherals on, TA=85℃	48
Run mode supply current, code from FLASH, 48MHz	IDD		10.8	11.9	mA	VDD=VDDA=5.5V, HSI or HSE, PLL on, all peripherals on, TA=85℃	48
Run mode supply current, code from FLASH, 24MHz	IDD		7	7.7	mA	VDD=VDDA=5.5V, HSI or HSE, PLL on, all peripherals on, TA=85℃	48
Run mode supply current, code from RAM, 64MHz	IDD		12.5	13.7	mA	VDD=VDDA=5.5V, HSI or HSE, PLL on, all peripherals on, TA=85℃	48
Sleep mode supply current, 64MHz	IDD		9.2	10.2	mA	VDD=VDDA=5.5V, HSI or HSE, PLL on, TA=85℃	48
DeepSleep supply current, regulator run, all oscillators off	IDD		0.6	8	μA	VDD=VDDA=3.6V, TA=85℃	49
DeepSleep supply current, regulator run, LSI and IWDT on	IDD		1.7	9	μA	VDD=VDDA=3.6V, TA=85℃	49
DeepSleep supply current, regulator run, LSE on	IDD		1.3	8.8	μA	VDD=VDDA=3.6V, TA=85℃	49
Wake-up time from DeepSleep	tWUDEEP		4	5	μs	regulator in run mode, VDD=VDDA=3.3V	51
User external HSE clock source frequency	fHSE_EXT	1		32	MHz		52
HSE oscillator frequency	fOSC_IN	4	8	32	MHz		53
HSE startup time	tsu(HSE)		2		ms	VDD stable	53
LSE startup time	tsu(LSE)		1.5		s	VDD stable	53
HSI frequency	fHSI		48		MHz		54
HSI factory calibration accuracy	ACCHSI	-2		2	%	TA = -40℃ ~ +85℃	54
HSI factory calibration accuracy	ACCHSI	-0.5		0.5	%	TA = +25℃	54
HSI oscillator setup time	tSU(HSI)	3		5	μs		54
LSI frequency	fLSI		32.8		kHz		54
LSI factory calibration accuracy	ACCLSI	-3		3	%	TA = -40℃ ~ +85℃	54
LSI factory calibration accuracy	ACCLSI	-1		1	%	TA = +25℃	54
LSI oscillator setup time	tSU(LSI)			50	μs		54
RC10K frequency	fRC10K		8.5		kHz		54
RC10K factory accuracy	ACCRC10K	-50		50	%	TA = -40℃ ~ +85℃	54
RC10K factory accuracy	ACCRC10K	-20		20	%	TA = +25℃	54
RC150K frequency	fRC150K		120		kHz		55
RC150K factory accuracy	ACCRC150K	-50		50	%	TA = -40℃ ~ +85℃	55
RC150K factory accuracy	ACCRC150K	-20		20	%	TA = +25℃	55
PLL input frequency	fPLL_IN	4		24	MHz		55
PLL output frequency	fPLL_OUT	8		64	MHz		55
PLL lock time	tLOCK		100	200	μs		55
PLL period jitter	JitterPLL			300	ps		55
FLASH 32-bit programming time	tprog32		51		μs	TA = -40℃ ~ +85℃	56
FLASH page erase time	tERASE		4.6		ms	TA = -40℃ ~ +85℃	56
FLASH mass erase time	tME		35		ms	TA = -40℃ ~ +85℃	56
FLASH programming supply current, write mode	IDD			3.5	mA		56
FLASH programming supply current, erase mode	IDD			2	mA		56
FLASH programming voltage	Vprog	1.65		5.5	V		56
FLASH endurance	NNED	20000			cycles	TA = -40℃ ~ +85℃	56
FLASH data retention	tRET	100			years	TA = 25℃	56
FLASH data retention	tRET	25			years	TA = 85℃	56
ESD human body model voltage	VESD(HBM)			8	kV	TA = +25℃, JESD22-A115C	56
ESD charged device model voltage	VESD(CDM)			2	kV	TA = +25℃, JESD22-A115C	56
Schmitt trigger hysteresis TC and TTa I/O	Vhys		400		mV		57
Weak pull-up equivalent resistance	RPU	50	80	180	kΩ	VIN = VSS	57
Weak pull-down equivalent resistance	RPD	20	30	45	kΩ	VIN = VDDIOx	57
I/O pin capacitance	CIO			5	pF		57
Output high voltage, sourcing 10mA	VOH	3.02			V	Sourcing 10mA, VDD = 3.3V	58
Output high voltage, sourcing 20mA	VOH	2.7			V	Sourcing 20mA, VDD = 3.3V	58
Output low voltage, sinking 10mA	VOL			0.23	V	Sinking 10mA, VDD = 3.3V	58
Output low voltage, sinking 20mA	VOL			0.45	V	Sinking 20mA, VDD = 3.3V	58
Maximum output frequency	fmax(IO)out			50	MHz	CL = 30pF, VDDIOx ≥ 2.7V	59
Maximum output frequency	fmax(IO)out			30	MHz	CL = 50pF, VDDIOx ≥ 2.7V	59
Maximum output frequency	fmax(IO)out			20	MHz	CL = 50pF, 2.4V ≤ VDDIOx < 2.7V	59
Output fall time	tf(IO)out			5	ns	CL = 30pF, VDDIOx ≥ 2.7V	59
Output rise time	tr(IO)out			5	ns	CL = 30pF, VDDIOx ≥ 2.7V	59
NRST weak pull-up equivalent resistance	RPU	7	8	9	kΩ	VIN = VSS	60
Required minimum reset pulse width	VF(NRST)	20			μs		60
ADC supply voltage when ADC on	VDDA	1.65		5.5	V		61
ADC clock frequency	fADC		24		MHz		61
ADC sampling rate	fS			1	MHz		61
ADC external trigger frequency	fTRIG			800	kHz	fADC = 24MHz	61
ADC input impedance direct or buffered	RAIN			100	kΩ		61
ADC sampling time	tS	5		10	1/fADC		61
ADC total conversion time including sampling	tCONV	24		29	1/fADC		61
ADC total error	ET		2.5	3	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~ +85℃	62
ADC offset error	EO		1.5	2.4	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~ +85℃	62
ADC gain error	EG		2.2	2.7	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~ +85℃	62
ADC differential nonlinearity	DNL		0.5	1	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~ +85℃	62
ADC integral nonlinearity	INL		1	3	LSB	fADC = 24MHz, VDDA = 1.65V ~ 5.5V, TA = -40℃ ~ +85℃	62
Temperature sensor linearity	TL		2	5	℃	VSENSE vs temperature	63
Temperature sensor average slope	Avg_Slope	2.66	2.69	2.72	mV / ℃		63
Temperature sensor voltage at 25℃	V25	0.77	0.79	0.8	V	25℃ ±5℃	63
Temperature sensor follower setup time	tSTART			45	μs		63
Temperature reading ADC sampling time	tS_temp	5			μs		63
Comparator analog supply voltage	VDDA	1.65		5.5	V		64
Comparator input voltage range	VIN	0			V	up to VDDA	64
Comparator offset error	Voffset	-3		10	mV		64
Comparator threshold voltage temperature coefficient	dThreshold/dt		40	80	ppm/℃	VDD = 3.3V, -40℃ < TA < +85℃, V- = (n/64)×Vref	64
LCD high drive resistance	RH	1000	1200	1400	kΩ		65
LCD low drive resistance	RL	70	90	110	kΩ		65
LCD voltage deviation	ΔVXX	-100		100	mV	-40℃ < TA < +85℃	65
Maximum timer count period	tMAX_COUNT			65536	tTIMCLK		66
I2C SCL clock low time, standard mode 100K	tw(SCLL)	4.7			μs	standard-mode 100K	67
I2C SCL clock low time, fast mode 400K	tw(SCLL)	1.25			μs	fast-mode 400K	67
I2C SCL clock low time, fast mode plus 1M	tw(SCLL)	0.5			μs	high-speed mode 1M	67
I2C SCL clock high time, standard mode 100K	tw(SCLH)	4			μs	standard-mode 100K	67
I2C SCL clock high time, fast mode 400K	tw(SCLH)	0.6			μs	fast-mode 400K	67
I2C SCL clock high time, high-speed mode 1M	tw(SCLH)	0.26			μs	high-speed mode 1M	67

CAD (KiCad official)

Symbol: CW32L083VCT6
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: cw32l083vct6-etched.step / cw32l083vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32l083vct6.step / cw32l083vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: CW datasheet (83 pp, sha256 7673e3c02dbf8cdf, retrieved 2026-11-02, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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CW32L083VCT6

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