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CW32L083MCT6

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CW Microcontrollers (MCU/MPU/SOC), LQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscw32l083mct6factory-2.0.0extractor-text

Verified CW32L083MCT6

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 80 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CW32L083MCT6 · LQFP-80(12x12) · 80 pins
  • ✓copper: 80 copper pads, none touching another net
  • ✓datasheet: all 80 pin names found in the 83-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: LQFP-80_12x12mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_s6wimjl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.75)
  • ✓pads: 80 pins = 80 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 80 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 76 kB, viewers/symbol.html 50 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cw32l083mct6.kicad_sym✓ cw32l083mct6.kicad_mod✓ cw32l083mct6.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cw32l083mct6: viewers rendered from the public page · Ray
cw32l083mct6-etched.glb cw32l083mct6: factory component page (tier=lcsc) · Ray
cw32l083mct6-etched.step cw32l083mct6: factory component page (tier=lcsc) · Ray
cw32l083mct6-hero.glb cw32l083mct6: hero GLB from the etched model (keeps the MPN mark) · Ray
cw32l083mct6-hero.overlay.json cw32l083mct6: hero GLB from the etched model (keeps the MPN mark) · Ray
cw32l083mct6.glb Publish 0.1.0 · Ray
cw32l083mct6.kicad_mod Publish 0.1.0 · Ray
cw32l083mct6.kicad_sym Publish 0.1.0 · Ray
cw32l083mct6.lbr Publish 0.1.0 · Ray
cw32l083mct6.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 80 pins · Ray

CW32L083MCT6

CW · Microcontrollers (MCU/MPU/SOC) · LQFP-80(12x12)

CW32L083MCT6 from CW, in a LQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Vcore power_out Internal core-logic supply node (VCORE) shown in the power system figure, to be decoupled with filter capacitors placed close to the pin.
2 PC13 bidirectional Standard I/O (TC) with alternate functions PLL_OUT, RTC_1Hz, UART1_CTS, RTC_OUT, BTIM_ETR, GTIM3_ETR and RTC_TAMP.
3 PC14 bidirectional Standard I/O (TC) that serves as the LSE oscillator input OSC32_IN; alternates include AUTOTRIM_ETR, GTIM4_CH4, UART1_RTS and UART4_TXD.
4 PC15 bidirectional Standard I/O (TC) that serves as the LSE oscillator output OSC32_OUT; alternates include HSE_OUT, GTIM4_CH3, UART4_RXD and SPI2_MOSI.
5 PF09 bidirectional Standard I/O (TC) with alternate functions UART2_TXD, UART3_RXD, BTIM3_TOGP, RTC_OUT, GTIM1_CH1 and HCLK_OUT.
6 PF10 bidirectional Standard I/O (TC) with alternate functions UART2_RXD, UART3_TXD, BTIM3_TOGN, HSI_OUT, GTIM1_CH2 and MCO_OUT.
7 PF00 bidirectional Standard I/O (TC) that serves as the HSE crystal/ceramic oscillator input OSC_IN (4 to 32 MHz); alternates include AUTOTRIM_ETR, GTIM4_CH2 and I2C1_SDA.
8 PF01 bidirectional Standard I/O (TC) that serves as the HSE crystal/ceramic oscillator output OSC_OUT; alternates include LSE_OUT, GTIM4_CH1 and I2C1_SCL.
9 NRST input Chip reset input with an internal pull-up of 7 to 9 kΩ and a minimum reset pulse width of 20 µs.
10 PC00 bidirectional Analog-capable I/O (TTa) with ADC/LCD SEG23 function and alternates UART4_CTS, GTIM2_CH4, SPI1_CS, LPTIM_CH1 and ATIM_CH1A.
11 PC01 bidirectional Analog-capable I/O (TTa) with LCD SEG22 function and alternates UART4_RTS, GTIM2_CH3, SPI1_SCK and LPTIM_OUT.
12 PC02 bidirectional Analog-capable I/O (TTa) with LCD SEG21 function and alternates UART4_RXD, GTIM2_CH2, SPI1_MISO and LPTIM_CH2.
13 PC03 bidirectional Analog-capable I/O (TTa) with LCD SEG20 function and alternates UART4_TXD, GTIM2_CH1, SPI1_MOSI and LPTIM_ETR.
14 PF02 bidirectional Standard I/O (TC) with alternate functions UART5_CTS, LVD_OUT, LSI_OUT, GTIM3_TOGP and MCO_OUT.
15 VSSA power_in Analog ground for the ADC, reset circuit, RC oscillator and PLL.
16 VDDA power_in Analog supply of 1.65 V to 5.5 V for the ADC, reset circuit, internal RC oscillator and PLL, which must be greater than or equal to VDD.
17 PF08 bidirectional Standard I/O (TC) with alternate functions UART5_RTS, PLL_OUT, PCLK_OUT and GTIM3_TOGN.
18 PA00 bidirectional Analog-capable I/O (TTa) with ADC_AIN0, VC1_CH0 and LVD_CH1 functions and alternates UART3_CTS, UART6_CTS, RTC_TAMP and SPI2_MISO.
19 PA01 bidirectional Analog-capable I/O (TTa) with ADC_AIN1, VC1_CH1 and SEG19 functions and alternates UART3_RTS, UART6_RTS, I2C2_SCL and SPI2_MOSI.
20 PA02 bidirectional Analog-capable I/O (TTa) with ADC_AIN2, VC1_CH2 and SEG18 functions and alternates UART3_TXD, UART6_TXD, I2C2_SDA and SPI2_SCK.
21 PA03 bidirectional Analog-capable I/O (TTa) with ADC_AIN3, VC1_CH3 and SEG17 functions and alternates UART3_RXD, UART6_RXD, PCLK_OUT and SPI2_CS.
22 PF04 bidirectional Standard I/O (TC) with alternate functions UART1_TXD, GTIM4_CH2 and UART5_RXD.
23 PF05 bidirectional Standard I/O (TC) with alternate functions UART1_RXD, BTIM_ETR, UART5_TXD and AUTOTRIM_ETR.
24 PA04 bidirectional Analog-capable I/O (TTa) with ADC_AIN4 and VC1_CH4 functions and alternates UART4_TXD, UART2_CTS, I2C2_SCL, HCLK_OUT and SPI1_CS.
25 PA05 bidirectional Analog-capable I/O (TTa) with ADC_AIN5 and VC1_CH5 functions and alternates GTIM2_ETR, UART2_RTS, I2C2_SDA and SPI1_SCK.
26 PA06 bidirectional Analog-capable I/O (TTa) with ADC_AIN6, VC1_CH6 and SEG16 functions and alternates GTIM3_CH1, UART2_TXD, VC1_OUT and SPI1_MISO.
27 PA07 bidirectional Analog-capable I/O (TTa) with ADC_AIN7, VC1_CH7 and SEG15 functions and alternates GTIM4_CH1, UART2_RXD, VC2_OUT and SPI1_MOSI.
28 PC04 bidirectional Analog-capable I/O (TTa) with ADC_AIN8 and SEG14 functions and alternates UART1_TXD, UART6_RXD, IR_OUT and LSI_OUT.
29 PC05 bidirectional Analog-capable I/O (TTa) with ADC_AIN9 and SEG13 functions and alternates UART1_RXD, UART6_TXD, MCO_OUT, LPTIM_ETR and LPTIM_OUT.
30 PB00 bidirectional Analog-capable I/O (TTa) with ADC_AIN10/ExRef, VC2_CH0, LVD_CH2 and SEG12 functions and alternates UART5_RXD, UART1_CTS, I2C2_SCL and HSIOSC_OUT.
31 PB01 bidirectional Analog-capable I/O (TTa) with ADC_AIN11, VC2_CH1 and SEG11 functions and alternates UART5_TXD, UART1_RTS, I2C2_SDA and GTIM4_TOGP.
32 PB02 bidirectional Analog-capable I/O (TTa) with ADC_AIN12 and VC2_CH2 functions and alternates UART2_CTS, UART1_TXD, LPTIM_OUT and GTIM4_TOGN.
33 PE12 bidirectional Analog-capable I/O (TTa) with SEG43 function and alternates UART3_TXD, GTIM2_CH4, SPI2_CS and GTIM3_CH4.
34 PE13 bidirectional Analog-capable I/O (TTa) with SEG42 function and alternates UART3_RXD, GTIM2_CH3, SPI2_SCK and GTIM4_CH2.
35 PE14 bidirectional Analog-capable I/O (TTa) with SEG41 function and alternates UART2_TXD, GTIM2_CH2, SPI2_MISO and GTIM4_CH3.
36 PE15 bidirectional Analog-capable I/O (TTa) with SEG40 function and alternates UART2_RXD, GTIM2_CH1, SPI2_MOSI and GTIM4_CH4.
37 PB10 bidirectional Analog-capable I/O (TTa) with VC2_CH3 and SEG10 functions and alternates UART2_RTS, UART4_RXD, I2C1_SCL, I2C2_SCL and SPI2_SCK.
38 PB11 bidirectional Analog-capable I/O (TTa) with LVD_CH3 and SEG9 functions and alternates GTIM4_ETR, UART4_TXD, I2C1_SDA, I2C2_SDA and BTIM_ETR.
39 VSS power_in Digital ground.
40 VDD power_in Digital supply of 1.65 V to 5.5 V for I/O and the internal regulator; all VDD pins must be supplied at the same voltage.
41 PB12 bidirectional Analog-capable I/O (TTa) with SEG8 function and alternates GTIM2_TOGP, GTIM4_CH4, LSE_OUT, SPI2_CS and SPI1_CS.
42 PB13 bidirectional Analog-capable I/O (TTa) with SEG7 function and alternates GTIM2_TOGN, GTIM4_CH3, I2C2_SCL, SPI2_SCK and SPI1_SCK.
43 PB14 bidirectional Analog-capable I/O (TTa) with SEG6 function and alternates GTIM2_CH1, GTIM4_CH2, I2C2_SDA, SPI2_MISO and RTC_OUT.
44 PB15 bidirectional Analog-capable I/O (TTa) with SEG5 function and alternates GTIM2_CH2, GTIM4_CH1, BTIM2_TOGN, SPI2_MOSI and RTC_1Hz.
45 PD08 bidirectional Analog-capable I/O (TTa) with SEG39 function and alternates GTIM2_CH3, LPTIM_OUT, UART1_TXD, SPI2_CS and GTIM1_CH1.
46 PD09 bidirectional Analog-capable I/O (TTa) with SEG38 function and alternates GTIM2_CH4, LPTIM_CH2, UART1_RXD, SPI2_SCK and GTIM1_CH2.
47 PD10 bidirectional Analog-capable I/O (TTa) with SEG37 function and alternates UART5_TXD, LPTIM_CH1, GTIM4_CH1, SPI2_MISO and GTIM1_CH3.
48 PD11 bidirectional Analog-capable I/O (TTa) with SEG36 function and alternates UART5_RXD, LPTIM_ETR, GTIM4_CH2, SPI2_MOSI and GTIM1_CH4.
49 PC06 bidirectional Analog-capable I/O (TTa) with SEG4 function and alternates UART4_RXD, UART3_TXD, BTIM2_TOGP, GTIM2_CH4 and ATIM_CH1B.
50 PC07 bidirectional Analog-capable I/O (TTa) with SEG3 function and alternates UART4_TXD, UART3_RXD, BTIM2_TOGN, GTIM2_CH3 and ATIM_CH2B.
51 PC08 bidirectional Analog-capable I/O (TTa) with SEG2 function and alternates UART4_CTS, UART6_TXD, GTIM4_ETR, GTIM2_CH2 and ATIM_CH3B.
52 PC09 bidirectional Analog-capable I/O (TTa) with SEG1 function and alternates UART4_RTS, UART6_RXD, I2C1_SDA, GTIM2_CH1 and ATIM_ETR.
53 PA08 bidirectional Analog-capable I/O (TTa) with VC2_CH4 and SEG0 functions and alternates LPTIM_ETR, UART1_TXD, BTIM2_TOGP, MCO_OUT and LVD_OUT.
54 PA09 bidirectional Analog-capable I/O (TTa) with VC2_CH5 and COM0 functions and alternates UART3_TXD, UART1_RXD, I2C1_SCL, BTIM1_TOGN and SPI1_CS.
55 PA10 bidirectional Analog-capable I/O (TTa) with VC2_CH6 and COM1 functions and alternates UART3_RXD, UART1_CTS, I2C1_SDA, BTIM1_TOGP and SPI1_SCK.
56 PA11 bidirectional Analog-capable I/O (TTa) with VC2_CH7 and COM2 functions and alternates UART3_CTS, UART1_RTS, I2C2_SCL, VC1_OUT and SPI1_MISO.
57 PA12 bidirectional Analog-capable I/O (TTa) with COM3 function and alternates UART3_RTS, BTIM_ETR, I2C2_SDA, VC2_OUT and SPI1_MOSI.
58 PA13/SWDIO bidirectional Standard I/O (TC) that is configured as the SWD data line SWDIO after reset, with the internal pull-up enabled; alternates include I2C1_SDA, UART1_RXD, UART2_TXD and IR_OUT.
59 PF06 bidirectional Standard I/O (TC) with alternate functions UART6_CTS, I2C1_SCL, GTIM4_TOGP, UART2_CTS, I2C2_SCL, GTIM3_TOGP and BTIM3_TOGN.
60 PF07 bidirectional Standard I/O (TC) with alternate functions UART6_RTS, I2C1_SDA, GTIM4_TOGN, UART2_RTS, I2C2_SDA, GTIM3_TOGN and BTIM3_TOGP.
61 PA14/SWCLK bidirectional Standard I/O (TC) that is configured as the SWD clock SWCLK after reset, with the internal pull-up enabled; alternates include UART3_TXD, I2C1_SCL, UART1_TXD, UART2_RXD and I2C2_SDA.
62 PA15 bidirectional Analog-capable I/O (TTa) with SEG55 function and alternates UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_TXD and SPI1_CS.
63 PC10 bidirectional Analog-capable I/O (TTa) with SEG31/COM4 functions and alternates UART4_TXD, GTIM3_CH1, HCLK_OUT, BTIM1_TOGP and VC1_OUT.
64 PC11 bidirectional Analog-capable I/O (TTa) with SEG30/COM5 functions and alternates UART4_RXD, GTIM3_CH2, IR_OUT, BTIM1_TOGN and VC2_OUT.
65 PC12 bidirectional Analog-capable I/O (TTa) with SEG29/COM6 functions and alternates UART5_TXD, PCLK_OUT, LVD_OUT, UART6_RXD and PLL_OUT.
66 PD00 bidirectional Standard I/O (TC) with alternate functions UART6_RXD, I2C2_SCL, AUTOTRIM_ETR, SPI2_CS and MCO_OUT.
67 PD01 bidirectional Standard I/O (TC) with alternate functions UART6_TXD, I2C2_SDA, RTC_1Hz, SPI2_SCK and RTC_TAMP.
68 PD02 bidirectional Analog-capable I/O (TTa) with SEG28/COM7 functions and alternates UART5_RXD, GTIM4_CH1, BTIM_ETR, UART6_TXD and RTC_1Hz.
69 PD03 bidirectional Analog-capable I/O (TTa) with SEG54 function and alternates UART6_CTS, I2C2_SCL, VC1_OUT, SPI2_MISO and GTIM1_CH3.
70 PD04 bidirectional Standard I/O (TC) with alternate functions UART6_RTS, I2C2_SDA, VC2_OUT, SPI2_MOSI, GTIM1_CH4 and ATIM_CH3A.
71 PB03 bidirectional Analog-capable I/O (TTa) with SEG27/VLCD4 functions and alternates UART3_RTS, GTIM2_CH2, UART4_CTS, UART2_TXD and SPI1_SCK.
72 PB04 bidirectional Analog-capable I/O (TTa) with SEG26/VLCD3 functions and alternates UART3_CTS, GTIM4_ETR, UART4_RTS, UART2_RXD and SPI1_MISO.
73 PB05 bidirectional Analog-capable I/O (TTa) with SEG25/VLCD2 functions and alternates UART4_RXD, GTIM3_CH4, LPTIM_CH1, UART2_RTS and SPI1_MOSI.
74 PB06 bidirectional Analog-capable I/O (TTa) with SEG24/VLCD1 functions and alternates UART6_TXD, GTIM3_CH3, LPTIM_ETR, I2C1_SCL and SPI2_MOSI.
75 PB07 bidirectional Analog-capable I/O (TTa) with alternate functions UART6_RXD, GTIM3_CH2, LPTIM_CH2, I2C1_SDA, SPI2_MISO, GTIM1_TOGN and ATIM_CH3A.
76 PF03/BOOT input Dedicated BOOT pin sampled at startup to select between the internal Bootloader and running the user program.
77 PB08 bidirectional Analog-capable I/O (TTa) with SEG53 function and alternates I2C1_SCL, GTIM3_CH1, UART5_TXD, GTIM4_CH2 and SPI2_SCK.
78 PB09 bidirectional Analog-capable I/O (TTa) with SEG52 function and alternates I2C1_SDA, GTIM4_CH1, UART5_RXD, IR_OUT and SPI2_CS.
79 VSS power_in Digital ground.
80 VDD power_in Digital supply of 1.65 V to 5.5 V for I/O and the internal regulator; all VDD pins must be supplied at the same voltage.

Key specifications

Parameter Value
Manufacturer CW
Package LQFP-80(12x12)
Category Embedded Processors & Controllers
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Main supply voltage VDD-VSS VDD - VSS -0.3 6 V 45
Analog supply voltage VDDA-VSS VDDA-VSS -0.3 6 V 45
Maximum allowed difference when VDD is above VDDA VDD-VDDA 0.3 V VDD greater than VDDA 45
Sum of sink current, all VDD supply lines (inflow) ΣIVDD 120 mA 45
Sum of source current, all VSS lines (outflow) ΣIVSS -120 mA 45
Sink current per single VDD supply line IVDD(PIN) 100 mA 45
Source current per single VSS line IVSS(PIN) -100 mA 45
Sink current, single I/O or control pin IIO(PIN) 25 mA 45
Source current, single I/O or control pin IIO(PIN) -25 mA 45
Sink current, sum of all I/O and control pins ΣIIO(PIN) 80 mA 45
Source current, sum of all I/O and control pins ΣIIO(PIN) -80 mA 45
Injection current, TC and RST pins IINJ(PIN) -5 5 mA 45
Injection current, TTa pins IINJ(PIN) -5 5 mA 45
Sum of injection current, all I/O and control pins ΣIINJ(PIN) -25 25 mA 45
Storage temperature range TSTG -65 150 ℃ 46
Maximum junction temperature TJ 105 ℃ 46
Internal AHB bus frequency fHCLK 0 64 MHz VDD ≥ 1.8V 47
Internal AHB bus frequency fHCLK 0 24 MHz 1.65V ≤ VDD < 1.8V 47
Standard operating voltage VDD 1.65 5.5 V 47
Analog operating voltage VDDA 1.65 5.5 V Must equal VDD 47
Ambient temperature, maximum power dissipation TA -40 85 ℃ Temperature grade 6 47
Ambient temperature, low power dissipation TA -40 105 ℃ Temperature grade 6; low power dissipation 47
Junction temperature range TJ -40 105 ℃ Temperature grade 6 47
VDD rise rate tVDD 0 μs/V 47
VDD fall rate tVDD 20 μs/V 47
Power-on/power-down reset threshold, falling edge VPOR/BOR 1.45 1.5 1.55 V Falling edge 48
Power-on/power-down reset threshold, rising edge VPOR/BOR 1.5 1.55 1.6 V Rising edge 48
Reset duration tRSTTEMPO 4 6.5 13 ms 48
Internal 1.5V reference voltage VREFINT1V5 1.485 1.5 1.515 V -40℃ < TA < +85℃ 48
Internal 2.5V reference voltage VREFINT2V5 2.475 2.5 2.525 V -40℃ < TA < +85℃ 48
Internal reference voltage distribution over full temperature range ΔVREFINT 10 mV VDDA = 3V 48
Internal reference voltage temperature coefficient TCoeff -60 60 ppm/℃ 48
Run-mode supply current, code running from FLASH, 64MHz IDD 13.6 15 mA VDD=VDDA=5.5V; TA=85℃; HSI or HSE clock, PLL on; all peripherals on; fHCLK 64MHz 49
Run-mode supply current, code running from RAM, 64MHz IDD 12.5 13.7 mA VDD=VDDA=5.5V; TA=85℃; HSI or HSE clock, PLL on; all peripherals on; fHCLK 64MHz 49
Sleep-mode supply current, code from FLASH or RAM, 64MHz IDD 9.2 10.2 mA VDD=VDDA=5.5V; TA=85℃; HSI or HSE clock, PLL on; fHCLK 64MHz 49
DeepSleep supply current, regulator in run mode, all oscillators off IDD 0.6 8 μA Typ at VDD=VDDA=3.6V; max at TA=85℃ 50
DeepSleep supply current, regulator in run mode, LSI and IWDT on IDD 1.7 9 μA Typ at VDD=VDDA=3.6V; max at TA=85℃ 50
DeepSleep supply current, regulator in run mode, LSE on IDD 1.3 8.8 μA Typ at VDD=VDDA=3.6V; max at TA=85℃ 50
HSE oscillator frequency (crystal/ceramic resonator) fOSC_IN 4 8 32 MHz 54
HSE user external clock source frequency fHSE_EXT 1 32 MHz Bypass mode 52
HSI factory calibration accuracy ACCHSI -2 2 % TA = -40℃ ~ +85℃ 55
LSI factory calibration accuracy ACCLSI -3 3 % TA = -40℃ ~ +85℃ 55
RC10K factory accuracy ACCRC10K -50 50 % TA = -40℃ ~ +85℃ 55
RC150K factory accuracy ACCRC150K -50 50 % TA = -40℃ ~ +85℃ 56
PLL input frequency fPLL_IN 4 24 MHz 56
PLL output frequency fPLL_OUT 8 64 MHz 56
PLL lock time tLOCK 100 200 μs 56
FLASH programming/erase supply voltage Vprog 1.65 5.5 V 57
FLASH endurance NNED 20000 次 TA = -40℃ ~ +85℃ 57
FLASH data retention at 85℃ tRET 25 年 TA = 85℃ 57
FLASH data retention at 25℃ tRET 100 年 TA = 25℃ 57
High-level output voltage VOH 3.02 V Sourcing 10mA, VDD = 3.3V 59
High-level output voltage VOH 2.7 V Sourcing 20mA, VDD = 3.3V 59
Low-level output voltage VOL 0.23 V Sinking 10mA, VDD = 3.3V 59
Low-level output voltage VOL 0.45 V Sinking 20mA, VDD = 3.3V 59
Weak pull-up equivalent resistance RPU 50 80 180 kΩ VIN = VSS 58
Weak pull-down equivalent resistance RPD 20 30 45 kΩ VIN = VDDIOx 58
NRST internal pull-up equivalent resistance RPU 7 8 9 kΩ VIN = VSS 61
Required minimum reset pulse width VF(NRST) 20 μs 61
ADC total unadjusted error ET -3 2.5 3 LSB fADC = 24MHz; VDDA = 1.65V ~ 5.5V; TA = -40℃ ~ +85℃ 63

CAD (KiCad official)

  • Symbol: CW32L083MCT6
  • Footprint: Package_QFP:LQFP-80_12x12mm_P0.5mm
  • 3D model: LQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: cw32l083mct6-etched.step / cw32l083mct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32l083mct6.step / cw32l083mct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CW datasheet (83 pp, sha256 7673e3c02dbf8cdf, retrieved 2026-11-13, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF