# CW32L031C8T6

**CW** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-48(7x7)

CW32L031C8T6 from CW, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vcore | power_in | Internal core voltage pin, which the datasheet shows as the @VCORE supply node of the power system and requires decoupling per Figure 7-3. |
| 2 | PC13 | bidirectional | Standard I/O (TC structure) with alternate functions UART1_TXD, RTC_1Hz, UART1_CTS, RTC_OUT, BTIM_ETR and RTC_TAMP. |
| 3 | PC14 | bidirectional | Standard I/O (TC structure) with alternate functions AWT_ETR, UART2_TXD, UART1_RTS, BTIM2_TOGN and UART2_RXD, and also serves as OSC32_IN. |
| 4 | PC15 | bidirectional | Standard I/O (TC structure) with alternate functions HSE_OUT, UART2_RXD, MCO_OUT, BTIM2_TOGP, UART2_TXD and UART1_RXD, and also serves as OSC32_OUT. |
| 5 | PF00 | bidirectional | Standard I/O (TC structure) with alternate functions AWT_ETR, UART3_TXD, I2C_SDA, BTIM1_TOGN, UART3_RXD and GTIM2_TOGP, and also serves as OSC_IN. |
| 6 | PF01 | bidirectional | Standard I/O (TC structure) with alternate functions LSE_OUT, UART3_RXD, I2C_SCL, BTIM1_TOGP, UART3_TXD and GTIM2_TOGN, and also serves as OSC_OUT. |
| 7 | NRST | input | Chip reset input; the datasheet specifies an internal pull-up of 7 to 9 kΩ and a minimum reset pulse width of 20 μs. |
| 8 | VSSA | power_in | Analog ground pin. |
| 9 | VDDA | power_in | Analog supply pin for the ADC, reset circuit and internal RC oscillators, specified at 1.65 V to 5.5 V and required to be greater than or equal to VDD. |
| 10 | PA00 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART3_CTS, UART2_CTS, RTC_TAMP, VC1_OUT, GTIM2_CH1 and GTIM2_ETR, and analog functions ADC_IN0, VC1_CH0 and LVD_CH1. |
| 11 | PA01 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART3_RTS, UART2_RTS, LVD_OUT, GTIM2_CH2 and RTC_TAMP, and analog functions ADC_IN1 and VC1_CH1. |
| 12 | PA02 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART3_TXD, UART2_TXD, VC2_OUT, GTIM2_CH3 and AWT_ETR, and analog functions ADC_IN2 and VC1_CH2. |
| 13 | PA03 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART3_RXD, UART2_RXD, GTIM2_CH2, PCLK_OUT, UART3_TXD, GTIM2_CH4 and ATIM_CH3A, and analog functions ADC_IN3 and VC1_CH3. |
| 14 | PA04 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions MCO_OUT, UART2_CTS, HCLK_OUT, SPI_CS, GTIM2_ETR and ATIM_CH2A, and analog functions ADC_IN4 and VC1_CH4. |
| 15 | PA05 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions GTIM2_ETR, UART2_RTS, BTIM2_TOGN, SPI_SCK, GTIM2_CH1 and ATIM_CH1A, and analog functions ADC_IN5, VC1_CH5 and VC2_CH0. |
| 16 | PA06 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_RXD, UART2_TXD, VC1_OUT, BTIM2_TOGP, SPI_MISO, GTIM1_CH1 and ATIM_BK, and analog functions ADC_IN6, VC1_CH6 and VC2_CH1. |
| 17 | PA07 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_TXD, UART2_RXD, VC2_OUT, BTIM1_TOGN, SPI_MOSI, GTIM1_CH2 and ATIM_CH1B, and analog functions ADC_IN7, VC1_CH7 and VC2_CH2. |
| 18 | PB00 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_RXD, UART1_CTS, UART2_TXD, BTIM1_TOGP, HSIOSC_OUT, GTIM1_CH3 and ATIM_CH2B, and analog functions ADC_IN8/ExRef, VC2_CH3 and LVD_CH2. |
| 19 | PB01 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_TXD, UART1_RTS, UART2_RXD, BTIM3_TOGN, GTIM1_CH4 and ATIM_CH3B, and analog functions ADC_IN9 and VC2_CH4. |
| 20 | PB02 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_CTS, UART1_TXD, HSE_OUT, UART1_RXD, BTIM3_TOGP, GTIM1_ETR and ATIM_CH1A, and analog functions ADC_IN10 and VC2_CH5. |
| 21 | PB10 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions UART2_RTS, UART1_RXD, I2C_SCL, UART1_TXD, GTIM2_CH3 and ATIM_CH2A, and analog functions ADC_IN11 and VC2_CH6. |
| 22 | PB11 | bidirectional | Analog-capable I/O (TTa structure) with alternate functions LSI_OUT, I2C_SDA, BTIM_ETR, GTIM2_CH4 and ATIM_CH3A, and analog functions ADC_IN12, VC2_CH7 and LVD_CH3. |
| 23 | VSS | power_in | Ground pin. |
| 24 | VDD | power_in | Digital supply pin for the I/O ports and internal regulator, specified at 1.65 V to 5.5 V, and all VDD pins must be powered at the same voltage. |
| 25 | PB12 | bidirectional | Standard I/O (TC structure) with alternate functions GTIM2_TOGP, LSE_OUT, SPI_CS, GTIM1_TOGP and ATIM_BK. |
| 26 | PB13 | bidirectional | Standard I/O (TC structure) with alternate functions GTIM2_TOGN, SPI_SCK, GTIM1_TOGN and ATIM_CH1B. |
| 27 | PB14 | bidirectional | Standard I/O (TC structure) with alternate functions GTIM2_CH1, SPI_MISO, RTC_OUT and ATIM_CH2B. |
| 28 | PB15 | bidirectional | Standard I/O (TC structure) with alternate functions GTIM2_CH2, BTIM2_TOGN, SPI_MOSI, RTC_1Hz and ATIM_CH3B. |
| 29 | PA08 | bidirectional | Standard I/O (TC structure) with alternate functions UART1_TXD, BTIM2_TOGP, MCO_OUT, LVD_OUT and ATIM_CH1A. |
| 30 | PA09 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_TXD, UART1_RXD, I2C_SCL, BTIM1_TOGN, SPI_CS, UART3_RXD and ATIM_CH2A. |
| 31 | PA10 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RXD, UART1_CTS, I2C_SDA, BTIM1_TOGP, SPI_SCK, UART3_TXD and ATIM_CH3A. |
| 32 | PA11 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_CTS, UART1_RTS, VC1_OUT, SPI_MISO and ATIM_GATE. |
| 33 | PA12 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RTS, BTIM_ETR, VC2_OUT, SPI_MOSI and ATIM_ETR. |
| 34 | PA13/SWDIO | bidirectional | Standard I/O (TC structure) that is configured as SWDIO after reset with the internal pull-up enabled; alternate functions include I2C_SDA, UART1_RXD, UART2_TXD and IR_OUT. |
| 35 | PF06 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_CTS, I2C_SCL, UART2_CTS and BTIM3_TOGN. |
| 36 | PF07 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RTS, I2C_SDA, UART2_RTS and BTIM3_TOGP. |
| 37 | PA14/SWCLK | bidirectional | Standard I/O (TC structure) that is configured as SWCLK after reset with the internal pull-up enabled; alternate functions include UART3_TXD, I2C_SCL, UART1_TXD and UART2_RXD. |
| 38 | PA15 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_RXD, SPI_CS, GTIM2_ETR and ATIM_CH1B. |
| 39 | PB03 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RTS, GTIM2_CH2, UART1_CTS, UART2_TXD, SPI_SCK, GTIM1_ETR and ATIM_CH2B. |
| 40 | PB04 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_CTS, UART1_RTS, UART2_CTS, SPI_MISO, GTIM1_CH1 and ATIM_CH3B. |
| 41 | PB05 | bidirectional | Standard I/O (TC structure) with alternate functions AWT_ETR, UART2_RTS, SPI_MOSI, GTIM1_CH2 and ATIM_CH1A. |
| 42 | PB06 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_TXD, UART3_RXD, I2C_SCL, GTIM1_TOGP and ATIM_CH2A. |
| 43 | PB07 | bidirectional | Standard I/O (TC structure) with alternate functions UART3_RXD, UART3_TXD, I2C_SDA, GTIM1_TOGN and ATIM_CH3A. |
| 44 | PF03/BOOT | input | Dedicated BOOT pin that selects at startup between running the internal Bootloader and running the user program. |
| 45 | PB08 | bidirectional | Standard I/O (TC structure) with alternate functions I2C_SCL, UART1_RXD, UART1_TXD, GTIM1_CH3 and ATIM_ETR. |
| 46 | PB09 | bidirectional | Standard I/O (TC structure) with alternate functions I2C_SDA, UART1_TXD, UART1_RXD, IR_OUT, GTIM1_CH4 and ATIM_BK. |
| 47 | VSS | power_in | Ground pin. |
| 48 | VDD | power_in | Digital power supply pin, specified at 1.65 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CW |
| Package | LQFP-48(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Standard operating voltage | VDD | 1.65 |  | 5.5 | V |  | 36 |
| Analog operating voltage | VDDA | 1.65 |  | 5.5 | V | 须等于 VDD | 36 |
| Internal AHB bus frequency | fHCLK | 0 |  | 48 | MHz | VDD ≥ 1.8V | 36 |
| Internal APB bus frequency | fPCLK | 0 |  | 48 | MHz | VDD ≥ 1.8V | 36 |
| Internal AHB bus frequency | fHCLK | 0 |  | 24 | MHz | 1.65V ≤ VDD < 1.8V | 36 |
| Internal APB bus frequency | fPCLK | 0 |  | 24 | MHz | 1.65V ≤ VDD < 1.8V | 36 |
| Power dissipation (LQFP48) | PD |  |  | 364 | mW | 温度标号 6：TA=85℃ LQFP48 | 36 |
| Ambient temperature (maximum power dissipation) | TA | -40 |  | 85 | ℃ | 温度标号 6, 最大功率耗散 | 36 |
| Ambient temperature (low power dissipation) | TA | -40 |  | 105 | ℃ | 低功率耗散 | 36 |
| Junction temperature range | TJ | -40 |  | 105 | ℃ | 温度标号 6 | 36 |
| VDD power-on/power-down reset threshold, falling edge | VPOR/BOR | 1.451 | 1.5 | 1.552 | V | 下降沿 | 37 |
| VDD power-on/power-down reset threshold, rising edge | VPOR/BOR | 1.502 | 1.55 | 1.6 | V | 上升沿 | 37 |
| BOR hysteresis | VBORhyst |  |  | 50 | mV | - | 37 |
| Reset duration | tRSTTEMPO | 4 | 6.5 | 13 | ms | - | 37 |
| Internal 1.5V reference voltage | VREFINT1V5 | 1.485 | 1.5 | 1.515 | V | -40℃ < TA < +85℃ | 37 |
| Internal 2.5V reference voltage | VREFINT2V5 | 2.475 | 2.5 | 2.525 | V | -40℃ < TA < +85℃ | 37 |
| Internal reference voltage distribution over full temperature range | ΔVREFINT |  |  | 101 | mV | VDDA = 3V | 37 |
| Internal reference voltage temperature coefficient | TCoeff | -601 |  | 601 | ppm/℃ |  | 37 |
| Run mode supply current, code from FLASH, all peripherals on, 48MHz | IDD |  | 7.2 | 8.2 | mA | VDD = VDDA = 5.5V, TA = 85℃, HSI or HSE clock, fHCLK 48MHz | 38 |
| Run mode supply current, code from FLASH, all peripherals off, 48MHz | IDD |  | 4.6 | 5.2 | mA | VDD = VDDA = 5.5V, TA = 85℃, HSI or HSE clock, fHCLK 48MHz | 38 |
| Run mode supply current, code from RAM, all peripherals on, 48MHz | IDD |  | 5.3 | 5.9 | mA | VDD = VDDA = 5.5V, TA = 85℃, HSI or HSE clock, fHCLK 48MHz | 38 |
| Sleep mode supply current, 48MHz, all peripherals on | IDD |  | 3.8 | 4.2 | mA | VDD = VDDA = 5.5V, TA = 85℃, HSI or HSE clock, fHCLK 48MHz | 38 |
| Sleep mode supply current, 48MHz, all peripherals off | IDD |  | 1.1 | 1.23 | mA | VDD = VDDA = 5.5V, TA = 85℃, HSI or HSE clock, fHCLK 48MHz | 38 |
| DeepSleep supply current, regulator in run mode, all oscillators off | IDD |  | 0.45 | 3.84 | μA | VDD = VDDA = 3.6V, TA = 85℃ | 39 |
| DeepSleep supply current, regulator in run mode, LSI and IWDT on | IDD |  | 1.11 | 4.65 | μA | VDD = VDDA = 3.6V, TA = 85℃ | 39 |
| Absolute max supply voltage VDD-VSS | VDD - VSS | -0.3 |  | 6 | V |  | 34 |
| Absolute max analog supply voltage VDDA-VSS | VDDA-VSS | -0.3 |  | 6 | V |  | 34 |
| Absolute max I/O input voltage | VIN | -0.3 |  | 0.3 | V | VIN relative to VSS and VDD+0.3V (upper limit VDD+0.3) | 34 |
| Total VDD supply line sink current sum | ΣIVDD |  |  | 120 | mA |  | 34 |
| Total VSS supply line source current sum | ΣIVSS | -120 |  |  | mA |  | 34 |
| Single I/O pin sink current | IIO(PIN) |  |  | 25 | mA |  | 34 |
| Single I/O pin output current | IIO(PIN) | -25 |  |  | mA |  | 34 |
| Storage temperature range | TSTG | -65 |  | 150 | ℃ |  | 35 |
| Maximum junction temperature | TJ |  |  | 105 | ℃ |  | 35 |
| Flash programming voltage | Vprog | 1.65 |  | 5.5 | V |  | 46 |
| ADC supply voltage when enabled | VDDA | 1.65 |  | 5.5 | V |  | 51 |
| HSI factory calibration accuracy | ACCHSI | -2 |  | 2 | % | TA = -40℃ ~ +85℃ | 45 |
| HSI factory calibration accuracy | ACCHSI | -0.5 |  | 0.5 | % | TA = +25℃ | 45 |
| Weak pull-up equivalent resistance | RPU | 45 | 75 | 220 | kΩ | VIN = VSS | 47 |
| Weak pull-down equivalent resistance | RPD | 16 | 30 | 50 | kΩ | VIN = VDDIOx | 47 |
| Output high voltage, sourcing current | VOH | 3.02 |  |  | V | Sourcing 10mA, VDD = 3.3V | 48 |
| Output high voltage, sourcing current | VOH | 2.7 |  |  | V | Sourcing 20mA, VDD = 3.3V | 48 |
| Output low voltage, sinking current | VOL |  |  | 0.23 | V | Sinking 10mA, VDD = 3.3V | 48 |
| Output low voltage, sinking current | VOL |  |  | 0.45 | V | Sinking 20mA, VDD = 3.3V | 48 |
| NRST weak pull-up equivalent resistance | RPU | 7 | 8 | 9 | kΩ | VIN = VSS | 50 |

## CAD (KiCad official)

- Symbol: `CW32L031C8T6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `cw32l031c8t6-etched.step` / `cw32l031c8t6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cw32l031c8t6.step` / `cw32l031c8t6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CW datasheet](docs/cw32l031c8t6-datasheet.pdf) (74 pp, sha256 `0e51efc1f45a11c9`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cw32l031c8t6-datasheet.pdf)