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CW32F030K8T7

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CW Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CW32F030K8T7

CW · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

CW32F030K8T7 from CW, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in I/O and internal regulator supply, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage.
2 PF00 bidirectional Standard TC I/O (CMOS/TTL compatible) with digital alternate functions selected by GPIOF_AFR (AWT_ETR, GTIM4_CH2, I2C1_SDA, BTIM1_TOGP, SPI2_SCK, GTIM2_TOGN, GTIM3_CH3) and analog function OSC_IN.
3 PF01 bidirectional Standard TC I/O with digital alternate functions selected by GPIOF_AFR (LSE_OUT, GTIM4_CH1, I2C1_SCL, SPI2_CS, GTIM3_CH4, GTIM2_TOGP, BTIM1_TOGN) and analog function OSC_OUT.
4 NRST input Chip reset input with internal pull-up of 7 to 9 kΩ; input low must be at or below 0.3VDD and the reset pulse must be at least 20 µs.
5 VDDA power_in Analog supply, 1.65 V to 5.5 V, for the ADC, reset circuit, internal RC oscillators and PLL; VDDA must always be greater than or equal to VDD, with VDD exceeding VDDA by no more than 0.3 V.
6 PA00 bidirectional TTa I/O with analog inputs ADC_IN0, VC1_CH0 and LVD_CH1, and digital alternate functions selected by GPIOA_AFR (UART3_CTS, UART2_CTS, RTC_TAMP, VC1_OUT, SPI2_MISO, GTIM2_CH1, GTIM2_ETR).
7 PA01 bidirectional TTa I/O with analog inputs ADC_IN1 and VC1_CH1, and digital alternate functions selected by GPIOA_AFR (UART3_RTS, UART2_RTS, I2C2_SCL, LVD_OUT, SPI2_MOSI, GTIM2_CH2, RTC_TAMP).
8 PA02 bidirectional TTa I/O with analog inputs ADC_IN2 and VC1_CH2, and digital alternate functions selected by GPIOA_AFR (UART3_TXD, UART2_TXD, I2C2_SDA, VC2_OUT, SPI2_SCK, GTIM2_CH3, AWT_ETR).
9 PA03 bidirectional TTa I/O with analog inputs ADC_IN3 and VC1_CH3, and digital alternate functions selected by GPIOA_AFR (UART3_RXD, UART2_RXD, GTIM2_CH2, PCLK_OUT, SPI2_CS, GTIM2_CH4, ATIM_CH3A).
10 PA04 bidirectional TTa I/O with analog inputs ADC_IN4 and VC1_CH4, and digital alternate functions selected by GPIOA_AFR (UART2_CTS, I2C2_SCL, HCLK_OUT, SPI1_CS, GTIM2_ETR, ATIM_CH2A).
11 PA05 bidirectional TTa I/O with analog inputs ADC_IN5, VC1_CH5 and VC2_CH0, and digital alternate functions selected by GPIOA_AFR (GTIM2_ETR, UART2_RTS, I2C2_SDA, BTIM2_TOGP, SPI1_SCK, GTIM2_CH1, ATIM_CH1A).
12 PA06 bidirectional TTa I/O with analog inputs ADC_IN6, VC1_CH6 and VC2_CH1, and digital alternate functions selected by GPIOA_AFR (GTIM3_CH1, UART2_TXD, VC1_OUT, BTIM2_TOGN, SPI1_MISO, GTIM1_CH1, ATIM_BK).
13 PA07 bidirectional TTa I/O with analog inputs ADC_IN7, VC1_CH7 and VC2_CH2, and digital alternate functions selected by GPIOA_AFR (GTIM4_CH1, UART2_RXD, VC2_OUT, BTIM1_TOGP, SPI1_MOSI, GTIM1_CH2, ATIM_CH1B).
14 PB00 bidirectional TTa I/O with analog inputs ADC_IN8/ExRef, VC2_CH3 and LVD_CH2, and digital alternate functions selected by GPIOB_AFR (UART2_RXD, UART1_CTS, I2C2_SCL, BTIM1_TOGN, HSI_OUT, GTIM1_CH3, ATIM_CH2B).
15 PB01 bidirectional TTa I/O with analog inputs ADC_IN9 and VC2_CH4, and digital alternate functions selected by GPIOB_AFR (UART2_TXD, UART1_RTS, I2C2_SDA, GTIM4_TOGN, BTIM3_TOGP, GTIM1_CH4, ATIM_CH3B).
16 VSS power_in Ground reference for the digital supply and I/O.
17 VDD power_in I/O and internal regulator supply, 1.65 V to 5.5 V; all VDD pins must be powered at the same voltage.
18 PA08 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART1_TXD, BTIM2_TOGN, MCO_OUT, LVD_OUT, GTIM3_ETR, ATIM_CH1A).
19 PA09 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART3_TXD, UART1_RXD, I2C1_SCL, BTIM1_TOGP, SPI1_CS, GTIM3_CH1, ATIM_CH2A).
20 PA10 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART3_RXD, UART1_CTS, I2C1_SDA, BTIM1_TOGN, SPI1_SCK, GTIM3_CH2, ATIM_CH3A).
21 PA11 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART3_CTS, UART1_RTS, I2C2_SCL, VC1_OUT, SPI1_MISO, GTIM3_CH3).
22 PA12 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART3_RTS, BTIM_ETR, I2C2_SDA, VC2_OUT, SPI1_MOSI, GTIM3_CH4, ATIM_ETR).
23 PA13/SWDIO bidirectional TC I/O configured as SWD data line SWDIO after reset with the internal pull-up enabled by default; alternate functions include I2C1_SDA, UART1_RXD, UART2_RXD, I2C2_SCL and IR_OUT.
24 PA14/SWCLK bidirectional TC I/O configured as SWD clock SWCLK after reset with the internal pull-up enabled by default; alternate functions include UART3_TXD, I2C1_SCL, UART1_TXD, UART2_TXD and I2C2_SDA.
25 PA15 bidirectional TC standard I/O with digital alternate functions selected by GPIOA_AFR (UART3_RXD, GTIM2_CH1, UART1_RXD, UART2_RXD, SPI1_CS, GTIM2_ETR, ATIM_CH1B).
26 PB03 bidirectional TC standard I/O with digital alternate functions selected by GPIOB_AFR (UART3_RTS, GTIM2_CH2, UART1_CTS, UART2_TXD, SPI1_SCK, GTIM1_ETR, ATIM_CH2B).
27 PB04 bidirectional TC standard I/O with digital alternate functions selected by GPIOB_AFR (UART3_CTS, GTIM4_ETR, UART1_RTS, UART2_CTS, SPI1_MISO, GTIM1_CH1, ATIM_CH3B).
28 PB05 bidirectional TC standard I/O with digital alternate functions selected by GPIOB_AFR (GTIM3_CH4, AWT_ETR, UART2_RTS, SPI1_MOSI, GTIM1_CH2, ATIM_CH1A).
29 PB06 bidirectional TC standard I/O with digital alternate functions selected by GPIOB_AFR (UART3_TXD, GTIM3_CH3, I2C1_SCL, GTIM4_CH4, SPI2_MOSI, GTIM1_TOGN, ATIM_CH2A).
30 PB07 bidirectional TC standard I/O with digital alternate functions selected by GPIOB_AFR (UART3_RXD, GTIM3_CH2, I2C1_SDA, GTIM4_CH3, SPI2_MISO, GTIM1_TOGP, ATIM_CH3A).
31 PF03/BOOT input Dedicated BOOT pin (I/O structure B) that selects at startup between running the internal Bootloader and running the user program; the datasheet lists no alternate functions for this pin.
32 VSS power_in Ground reference for the digital supply and I/O.

Key specifications

Parameter Value
Manufacturer CW
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD-VSS 外供主电源电压 VDD - VSS -0.3 6 V 34
VDDA-VSS 外供模拟电源电压 VDDA-VSS -0.3 6 V 34
VDD 大于 VDDA 时允许的最大差值 VDD-VDDA 0.3 V 34
不同 VDD 引脚间的压差 /ΔVDDx/ 0.05 V 34
不同 VSS 引脚间的压差 /VSSX-VSS/ 0.05 V 34
全部 VDD 供电线的灌电流总和（流入） ΣIVDD 120 mA 34
全部 VSS 供电线的拉电流总和（流出） ΣIVSS -120 mA 34
单个 VDD 供电线的灌电流总和（流入） IVDD(PIN) 100 mA 34
单个 VSS 供电线的拉电流总和（流出） IVSS(PIN) -100 mA 34
单个 I/O 或控制引脚灌入的电流 IIO(PIN) 25 mA 34
单个 I/O 或控制引脚输出的电流 IIO(PIN) -25 mA 34
TC 和 RST 引脚的注入电流 IINJ(PIN) -5 5 mA 34
TTa 引脚的注入电流 IINJ(PIN) -5 5 mA 34
全部 I/O 或控制引脚注入的电流总和 ΣIINJ(PIN) -25 25 mA 34
储存温度范围 TSTG -65 150 ℃ 35
最大结温 TJ 125 ℃ 35
内部 AHB 总线频率 fHCLK 0 64 MHz 36
内部 APB 总线频率 fPCLK 0 64 MHz 36
内部 AHB 总线频率 fHCLK 0 24 MHz VDD < 1.8V 36
内部 APB 总线频率 fPCLK 0 24 MHz VDD < 1.8V 36
标准工作电压 VDD 1.65 5.5 V 36
模拟工作电压 VDDA 1.65 5.5 V 须等于 VDD 36
I/O 输入电压 VIN -0.3 V TC I/O 36
环境温度（最大功率耗散） TA -40 105 ℃ 温度标号 7 36
环境温度（低功率耗散） TA -40 125 ℃ 低功率耗散 36
结温范围 TJ -40 125 ℃ 温度标号 7 36
功率耗散 LQFP32 PD 357 mW 温度标号 7：TA=105℃ 36
VDD 上升速率 tVDD 0 μs/V 36
VDD 下降速率 tVDD 20 μs/V 36
上电/掉电复位门限 下降沿 VPOR/BOR 1.45 1.5 1.55 V 37
上电/掉电复位门限 上升沿 VPOR/BOR 1.5 1.55 1.6 V 37
复位持续时间 tRSTTEMPO 2 2.5 3 ms 37
内部 1.5V 参考电压 VREFINT1V5 1.485 1.5 1.515 V -40℃ < TA < +105℃ 37
内部 2.5V 参考电压 VREFINT2V5 2.475 2.5 2.525 V -40℃ < TA < +105℃ 37
全温度范围内的内部参考电压分布 ΔVREFINT 10 mV VDDA = 3V 37
温度系数 TCoeff -60 60 ppm/℃ 37
编程电压 Vprog 1.65 5.5 V 46
供电电流（写模式） IDD 3.5 mA 46
供电电流（擦除模式） IDD 2 mA 46
寿命 NNED 20000 次 TA = -40℃ ~ +105℃ 46
数据保存期限 tRET 100 年 TA = 25℃ 46
数据保存期限 tRET 25 年 TA = 85℃ 46
数据保存期限 tRET 10 年 TA = 105℃ 46
静电放电电压（人体模型） VESD(HBM) 8 kV TA = +25℃，符合 JESD22-A115C 46
输入漏电流（数字模式） Iikg -0.1 0.1 μA 数字模式 VSS ≤ VIN ≤ VDDIOx 47
输入漏电流（TTa I/O 数字模式） Iikg 1 μA 数字模式 VDDIOx ≤ VIN ≤ VDDA 47
输入漏电流（TTa I/O 模拟模式） Iikg -0.2 0.2 μA 模拟模式 VSS ≤ VIN ≤ VDDA 47
弱上拉等效电阻 RPU 50 80 180 kΩ VIN = VSS 47
弱下拉等效电阻 RPD 20 30 45 kΩ VIN = VDDIOx 47
高电平输出电压源电流 VOH 3.02 V Sourcing 5mA, VDD = 3.3V 48
高电平输出电压源电流 VOH 2.7 V Sourcing 10mA, VDD = 3.3V 48
低电平输出电压灌电流 VOL 0.25 V Sinking 6mA, VDD = 3.3V 48
低电平输出电压灌电流 VOL 0.7 V Sinking 15mA, VDD = 3.3V 48
高电平输出电压双源电流 VOHD 3.02 V Sourcing 10mA, VDD = 3.3V 48
高电平输出电压双源电流 VOHD 2.7 V Sourcing 20mA, VDD = 3.3V 48
低电平输出电压双灌电流 VOLD 0.23 V Sinking 10mA, VDD = 3.3V 48
低电平输出电压双灌电流 VOLD 0.45 V Sinking 20mA, VDD = 3.3V 48
NRST 弱上拉等效电阻 RPU 7 8 9 kΩ VIN = VSS 50
要求的最短复位脉冲宽度 VF(NRST) 20 μs 50

CAD (KiCad official)

  • Symbol: CW32F030K8T7
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: cw32f030k8t7-etched.step / cw32f030k8t7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32f030k8t7.step / cw32f030k8t7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CW datasheet (72 pp, sha256 a3ae82a897ab1ca3, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF