component

CW32F003E4P7

Public Made by Adom

by adom

CW Microcontrollers (MCU/MPU/SOC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscw32f003e4p7factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cw32f003e4p7 / README.md
History Download
Ray Publish 0.1.0 e632bb4 8d ago

CW32F003E4P7

CW · Microcontrollers (MCU/MPU/SOC) · TSSOP-24

CW32F003E4P7 from CW, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PC00 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_RXD, UART1_TXD, SPI_SCK, ATIM_CH1A, GTIM_CH2, BTIM1_TOGP, HCLK_OUT, and analog functions ADC_AIN5 and VC2_CH6; high-impedance input after reset.
2 PC01 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_TXD, GTIM_ETR, SPI_MISO, ATIM_CH2A, GTIM_CH3, BTIM1_TOGN, VC1_OUT, and analog functions ADC_AIN6 and VC2_CH7; high-impedance input after reset.
3 PC02 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_RXD, IR_OUT, SPI_MOSI, ATIM_CH3A, GTIM_CH4, HCLK_OUT, AWT_ETR, and analog functions ADC_AIN7 and VC1_CH0; high-impedance input after reset.
4 NRST input Active-low chip reset input with internal pull-up of 7-9 kΩ; input low must be at most 0.3VDD and the reset pulse must be at least 20 µs.
5 PC03 bidirectional Standard I/O (TC, no analog function) with digital alternate functions UART1_TXD, SPI_CS, SPI_MISO, ATIM_CH3B, GTIM_CH3, GTIM_TOGP, ATIM_BK; high-impedance input after reset.
6 PB00 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_RXD, I2C_SDA, SPI_CS, ATIM_CH1B, GTIM_CH1, GTIM_TOGP, AWT_ETR, analog functions ADC_AIN8, VC1_CH1, and HEX_PB00; can also receive the external high-speed clock input to the HEX circuit (1-32 MHz).
7 PC04 bidirectional Standard I/O (TC, no analog function) with digital alternate functions UART1_RXD, IR_OUT, SPI_MOSI, ATIM_CH2B, GTIM_CH4, GTIM_TOGN; high-impedance input after reset.
8 PB01 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_TXD, LVD_OUT, I2C_SCL, ATIM_BK, GTIM_CH2, GTIM_TOGN, AWT_ETR, analog functions ADC_AIN9, VC1_CH2, and HEX_PB01; can also receive the external high-speed clock input to the HEX circuit (1-32 MHz).
9 VSS power_in Ground reference; all voltages in the datasheet are specified relative to VSS, and each VDD/VSS pair must be decoupled with a filter ceramic capacitor placed as close to the pins as possible.
10 PA02/SWDIO bidirectional Standard I/O (TC) with digital alternate functions UART1_RXD, UART2_TXD, I2C_SDA, GTIM_ETR, GTIM_CH3, VC2_OUT, AWT_ETR; after reset it is configured as the SWDIO debug function with internal pull-up enabled.
11 VDD power_in Supply voltage, 1.65 V to 5.5 V; all VDD pins must be powered and held at the same voltage.
12 PB07 bidirectional Standard I/O (TC, no analog function) with digital alternate functions UART2_RXD, UART1_TXD, SPI_SCK, GTIM_CH1, BTIM2_TOGN, BTIM_ETR; high-impedance input after reset.
13 PB06 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_TXD, I2C_SCL, SPI_CS, ATIM_CH1A, GTIM_TOGP, BTIM2_TOGP, HCLK_OUT, and analog functions ADC_AIN10 and LVD_CH1; high-impedance input after reset.
14 PB05 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_RXD, I2C_SDA, BTIM_ETR, ATIM_CH1B, GTIM_TOGN, BTIM2_TOGN, ATIM_BK, and analog functions ADC_AIN11 and VC1_CH3; high-impedance input after reset.
15 PB04 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_TXD, I2C_SCL, GTIM_ETR, ATIM_ETR, GTIM_CH1, BTIM3_TOGN, ATIM_BK, and analog functions ExRef and VC1_CH4; high-impedance input after reset.
16 PB03 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_RXD, I2C_SDA, PCLK_OUT, ATIM_CH2A, GTIM_CH2, BTIM3_TOGP, IR_OUT, and analog functions ADC_AIN12, VC1_CH5, and LVD_CH2; high-impedance input after reset.
17 PB02 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_TXD, UART2_CTS, SPI_CS, ATIM_CH2B, GTIM_CH3, BTIM1_TOGP, MCO_OUT, and analog functions ADC_AIN0, VC1_CH6, and VC2_CH0; high-impedance input after reset.
18 PA00 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_RXD, UART2_RTS, SPI_SCK, ATIM_CH3A, GTIM_CH4, BTIM1_TOGN, VC1_OUT, and analog functions VC1_CH7, VC2_CH1, and LVD_CH3; high-impedance input after reset.
19 PA01 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART2_TXD, VC2_OUT, SPI_MOSI, ATIM_CH3B, GTIM_CH1, BTIM2_TOGP, MCO_OUT, and analog functions ADC_AIN1 and VC2_CH2; high-impedance input after reset.
20 PA03 bidirectional Standard I/O (TC, no analog function) with digital alternate functions UART2_TXD, UART1_RXD, PCLK_OUT, ATIM_BK, GTIM_ETR, BTIM2_TOGP, LVD_OUT; high-impedance input after reset.
21 PA04 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_RXD, IR_OUT, SPI_MISO, ATIM_CH3B, GTIM_CH2, BTIM2_TOGN, GTIM_ETR, and analog functions ADC_AIN2 and VC2_CH3; high-impedance input after reset.
22 PA05/SWCLK bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_TXD, UART2_RXD, I2C_SCL, GTIM_CH4, BTIM_ETR, MCO_OUT; after reset it is configured as the SWCLK debug function with internal pull-up enabled.
23 PA06 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_CTS, UART2_TXD, I2C_SDA, ATIM_CH2B, GTIM_CH3, BTIM3_TOGP, LVD_OUT, and analog functions ADC_AIN3 and VC2_CH4; high-impedance input after reset.
24 PA07 bidirectional General-purpose I/O (TTa, analog-capable) with digital alternate functions UART1_RTS, UART2_RXD, VC1_OUT, ATIM_CH1B, GTIM_CH4, BTIM3_TOGN, ATIM_BK, and analog functions ADC_AIN4 and VC2_CH5; high-impedance input after reset.

Key specifications

Parameter Value
Manufacturer CW
Package TSSOP-24
Category Embedded Processors & Controllers
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD - VSS supply voltage (absolute maximum) VDD - VSS -0.3 6 V 29
VDD supply line sink current sum (inflow) IVDD(PIN) 100 mA 29
VSS supply line source current sum (outflow) IVSS(PIN) -100 mA 29
Single I/O or control pin sink current IIO(PIN) 25 mA 29
Single I/O or control pin source current IIO(PIN) -25 mA 29
Sum of all I/O or control pin sink currents ΣIIO(PIN) 80 mA 29
Sum of all I/O or control pin source currents ΣIIO(PIN) -80 mA 29
Injection current, TC and RST pins IINJ(PIN) -5 5 mA 29
Injection current, TTa pins IINJ(PIN) -5 5 mA 29
Sum of all I/O or control pin injection currents ΣIINJ(PIN) -25 25 mA 29
Storage temperature range TSTG -65 150 ℃ 29
Maximum junction temperature TJ 125 ℃ 29
ESD voltage, human body model VESD(HBM) 8 kV TA = +25℃, JESD22-A115C 38
ESD voltage, charged device model VESD(CDM) 2 kV TA = +25℃, JESD22-A115C 38
Internal AHB bus frequency fHCLK 0 48 MHz 30
Internal APB bus frequency fPCLK 0 48 MHz 30
Internal AHB bus frequency at low voltage fHCLK 0 24 MHz VDD < 1.8V 30
Internal APB bus frequency at low voltage fPCLK 0 24 MHz VDD < 1.8V 30
Standard operating supply voltage VDD 1.65 5.5 V 30
I/O input voltage, TC I/O (minimum; maximum VDD+0.3 is symbolic) VIN -0.3 V TC I/O 30
I/O input voltage, TTa I/O (minimum; maximum VDD+0.3 is symbolic) VIN -0.3 V TTa I/O 30
Ambient temperature (temperature code 7, maximum power dissipation) TA -40 105 ℃ temperature code 7; maximum power dissipation 30
Ambient temperature (low power dissipation) TA -40 125 ℃ low power dissipation 30
Junction temperature range TJ -40 125 ℃ temperature code 7 30
VDD rising rate tVDD 0 μs/V 30
VDD falling rate tVDD 20 μs/V 30
POR/BOR threshold, falling edge VPOR/BOR 1.45 1.5 1.55 V falling edge 31
POR/BOR threshold, rising edge VPOR/BOR 1.5 1.55 1.6 V rising edge 31
Reset duration tRSTTEMPO 2 2.5 3 ms 31
Internal 1.5V reference voltage VREFINT1V5 1.485 1.5 1.515 V -40℃ < TA < +105℃ 31
Internal 2.5V reference voltage VREFINT2V5 2.475 2.5 2.525 V -40℃ < TA < +105℃ 31
Internal reference voltage distribution over full temperature range ΔVREFINT 10 mV VDD = 3V 31
Internal reference voltage temperature coefficient TCoeff -60 60 ppm/℃ 31
Run mode supply current, code from FLASH, 48MHz IDD 5.5 6 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
Run mode supply current, code from FLASH, 24MHz IDD 4 4.5 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
Run mode supply current, code from RAM, 48MHz IDD 4.5 5 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
Run mode supply current, code from RAM, 24MHz IDD 2.5 3 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
Sleep mode supply current, 48MHz IDD 3 3.5 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
Sleep mode supply current, 24MHz IDD 1.8 2.2 mA VDD = 5.5V, HSI clock, all peripherals on, TA = 105℃ (max) 32
DeepSleep supply current, regulator in run mode, all oscillators off IDD 22 42 μA typ at VDD = 3.6V; max at TA = 105℃ 32
DeepSleep supply current, regulator in run mode, LSI and IWDT on IDD 24 45 μA typ at VDD = 3.6V; max at TA = 105℃ 32
Wake-up time from DeepSleep tWUDEEP 4 5 μs regulator in run mode; typ at VDD = 3.3V 35
I/O digital-mode input leakage, TC and TTa Iikg -0.1 0.1 μA digital mode, VSS ≤ VIN ≤ VDDIOx 39
I/O digital-mode input leakage, TTa Iikg 1 μA digital mode, VDDIOx ≤ VIN ≤ VDDA 39
I/O analog-mode input leakage, TTa Iikg -0.2 0.2 μA analog mode, VSS ≤ VIN ≤ VDDA 39
Weak pull-up equivalent resistance RPU 50 80 180 kΩ VIN = VSS 39
Weak pull-down equivalent resistance RPD 20 30 45 kΩ VIN = VDDIOx 39
High-level output voltage, sourcing 10mA VOH 3 V Sourcing 10mA, VDD = 3.3V 40
High-level output voltage, sourcing 20mA VOH 2.72 V Sourcing 20mA, VDD = 3.3V 40
Low-level output voltage, sinking 10mA VOL 0.22 V Sinking 10mA, VDD = 3.3V 40
Low-level output voltage, sinking 20mA VOL 0.42 V Sinking 20mA, VDD = 3.3V 40
NRST weak pull-up equivalent resistance RPU 7 8 9 kΩ VIN = VSS 42
Required minimum reset pulse width VF(NRST) 20 μs 42
HSI factory calibration accuracy ACCHSI -2 2 % TA = -40℃ ~ +105℃ 36
HSI factory calibration accuracy ACCHSI -0.5 0.5 % TA = +25℃ 36
LSI factory calibration accuracy ACCLSI -3 3 % TA = -40℃ ~ +105℃ 36
LSI factory calibration accuracy ACCLSI -1 1 % TA = +25℃ 36
RC10K factory accuracy ACCRC10K -50 50 % TA = -40℃ ~ +105℃ 36
RC10K factory accuracy ACCRC10K -20 20 % TA = +25℃ 36
FLASH program supply voltage Vprog 1.65 5.5 V 38

CAD (KiCad official)

  • Symbol: CW32F003E4P7
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cw32f003e4p7-etched.step / cw32f003e4p7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cw32f003e4p7.step / cw32f003e4p7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CW datasheet (58 pp, sha256 d9a466f1abc5af59, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF