component
CT425-HSN830MR
Public Made by Adomby adom
Allegro MicroSystems, LLC Current Sensors, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| ct425-hsn830mr-etched.step | 6h ago |
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| package.json | 6h ago |
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| README.md | 6h ago |
CT425-HSN830MR
Allegro MicroSystems, LLC · Current Sensors · SOIC-8
CT425-HSN830MR from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IP+ | passive | Input primary conductor (positive) carrying the current to be measured; pins 1 and 2 are internally common. |
| 2 | IP+ | passive | Input primary conductor (positive) carrying the current to be measured; pins 1 and 2 are internally common. |
| 3 | IP- | passive | Output primary conductor (negative) through which the measured current returns; pins 3 and 4 are internally common. |
| 4 | IP- | passive | Output primary conductor (negative) through which the measured current returns; pins 3 and 4 are internally common. |
| 5 | GND | power_in | Ground reference for the device. |
| 6 | FILTER | passive | Filter pin that sets the output noise cut-off frequency when an external capacitor is connected; leave unconnected if the filter is not used. |
| 7 | OUT | output | Analog output voltage representing the measured current, with drive capability of ±1.0 mA and capacitive load up to 100 pF. |
| 8 | VCC | power_in | Supply voltage, 4.75 V to 5.50 V recommended operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8 |
| Category | Magnetic Sensors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Current Range | IRANGE | -30 | 30 | A | 13 | ||
| Voltage Output Quiescent | VOQ | 2.495 | 2.5 | 2.505 | V | TA = 25°C, IP = 0 A | 13 |
| Total Output Error | ETOT | -1 | 1 | % FS | IP sweep from IP(MIN) to IP(MAX) | 13 | |
| Supply Current | ICC | 6 | 9 | mA | fBW = 1 MHz, no load, IP = 0 A | 7 | |
| OUT Maximum Drive Capability | IOUT | -1 | 1 | mA | OUT covers 10% to 90% of VCC span | 7 | |
| OUT Capacitive Load | CL_OUT | 100 | pF | 7 | |||
| OUT Voltage Linear Range, Typical | VOUT | 0.5 | 4.5 | V | VSIG_AC = ±2.00 V, VSIG_DC = +4.00 V | 7 | |
| Power-On Time | tON | 100 | 200 | µs | VCC ≥ 2.50 V | 7 | |
| Supply Voltage | VCC | -0.3 | 6 | V | Supply Voltage Strength | 4 | |
| Analog Input/Output Pins Maximum Voltage | VI/O | -0.3 | V | Upper limit VCC + 0.3 V (lower of VCC + 0.3 V or 6.0 V) | 4 | ||
| Current Carrying Conductor Maximum Current | ICCC(MAX) | 70 | A | TA = 25°C | 4 | ||
| Dielectric Surge Strength Test Voltage | VSURGE | 6 | kV | IEC 61000-4-5: Tested ±5 Pulses at 2/60 seconds, 1.2 µs (rise) and 50 µs (width) | 4 | ||
| Surge Strength Test Current | ISURGE | 3 | kA | Tested ±5 Pulses at 3/60 seconds, 8.0 µs (rise) and 20 µs (width) | 4 | ||
| Electrostatic Discharge Protection Level HBM | -2 | 2 | kV | Human Body Model (HBM) per JESD22-A114 | 4 | ||
| Electrostatic Discharge Protection Level CDM | -0.5 | 0.5 | kV | Charged Device Model (CDM) per JESD22-C101 | 4 | ||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage Temperature | TSTG | -65 | 155 | °C | 4 | ||
| Lead Soldering Temperature | TL | 260 | °C | 10 seconds | 4 | ||
| Supply Voltage Range | VCC | 4.75 | 5 | 5.5 | V | 4 | |
| Output Voltage Range | VOUT | 0 | V | Upper limit VCC | 4 | ||
| Output Current | IOUT | -1 | 1 | mA | 4 | ||
| Operating Ambient Temperature | TA | -40 | 25 | 125 | °C | Extended Industrial | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | CCC pins be connected to as much copper area as possible. It is | 21 |
CAD (KiCad official)
- Symbol:
CT425-HSN830MR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ct425-hsn830mr-etched.step/ct425-hsn830mr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ct425-hsn830mr.step/ct425-hsn830mr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (26 pp, sha256
243dacc9791f008c, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).