CT417-HSN820DR from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IP+	passive	Input primary conductor (positive) carrying the measured current through the integrated current carrying conductor.
2	IP+	passive	Input primary conductor (positive) carrying the measured current through the integrated current carrying conductor.
3	IP-	passive	Output primary conductor (negative) carrying the measured current out of the integrated current carrying conductor.
4	IP-	passive	Output primary conductor (negative) carrying the measured current out of the integrated current carrying conductor.
5	GND	power_in	Ground reference for the device.
6	FLT	output	Active low open drain fault output indicating OCD or UVLO; if not used, a 1.0 nF capacitor must be connected from the pin to ground, with a 100 kΩ pull-up to VCC when used.
7	OUT	output	Analog output voltage representing the measured current, with a maximum drive capability of ±1.0 mA and a capacitive load limit of 100 pF.
8	VCC	power_in	Supply voltage, recommended range 3.0 to 3.6 V with a 1.0 µF bypass capacitor.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	SOIC-8
Category	Magnetic Sensors
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage Strength	VCC	-0.3		6	V		3
Analog Input/Output Pins Maximum Voltage	VI/O	-0.3			V	Maximum is VCC + 0.3 V, lower of VCC + 0.3 V or 6.0 V	3
Current Carrying Conductor Maximum Current	ICCC(MAX)			70	A	TA = 25°C	3
Dielectric Surge Strength Test Voltage	VSURGE	6			kV	IEC 61000-4-5: Tested ±5 Pulses at 2/60 seconds, 1.2 µs (rise) and 50 µs (width)	3
Surge Strength Test Current	ISURGE	3			kA	Tested ±5 Pulses at 3/60 seconds, 8.0 µs (rise) and 20 µs (width)	3
Electrostatic Discharge Protection Level HBM		-2		2	kV	Human Body Model (HBM) per JESD22-A114	3
Electrostatic Discharge Protection Level CDM		-0.5		0.5	kV	Charged Device Model (CDM) per JESD22-C101	3
Junction Temperature	TJ	-40		150	°C		3
Storage Temperature	TSTG	-65		155	°C		3
Lead Soldering Temperature	TL			260	°C	10 seconds	3
Supply Voltage Range	VCC	3	3.3	3.6	V		3
Output Voltage Range	VOUT	0			V	0, VCC	3
Output Current	IOUT	-1		1	mA		3
Operating Ambient Temperature (Extended Industrial)	TA	-40	25	125	°C	Extended Industrial	3
Operating Ambient Temperature (Automotive)	TA	-40	25	125	°C	Automotive	3
Supply Current	ICC		6	9	mA	fBW = 1 MHz, no load, IP = 0 A	6
OUT Maximum Drive Capability	IOUT	-1		1	mA	OUT covers 10% to 90% of VCC span	6
OUT Capacitive Load	CL_OUT			100	pF		6
OUT Voltage Linear Range, Typical	VOUT	0.65		2.65	V	VSIG_AC = ±1.00 V, VSIG_DC = +2.00 V	6
FLT Voltage Low	VFLT#_OL	0		0.5	V	IFLT#_OUT ≤ 20 mA	6
Power-On Time	tON		100	200	µs	VCC ≥ 2.50 V	6
Current Range	IRANGE	0		20	A		10
Voltage Output Quiescent	VOQ	0.645	0.65	0.655	V	TA = 25°C, IP = 0 A	10
Total Output Error	ETOT	-3		3	% FS	IP sweep from IP(MIN) to IP(MAX)	10
Linearity Error	ELIN	-0.3		0.3	% FS	IP = IP(MAX), TA = -40°C to 125°C	10
Sensitivity Error	ESENS	-0.4		0.4	%	IP = IP(MAX), TA = 25°C	10
Sensitivity Error	ESENS	-3.3		3.3	%	IP = IP(MAX), TA = 125°C	10
Sensitivity Error	ESENS	-2.7		2.7	%	IP = IP(MAX), TA = -40°C	10
Offset Voltage Error	VOE	-6		6	mV	IP = 0 A, TA = 25°C	10
Offset Voltage Error	VOE	-31		31	mV	IP = 0 A, TA = 125°C	10
Offset Voltage Error	VOE	-22		22	mV	IP = 0 A, TA = -40°C	10
Total Error Including Lifetime Drift	ETOT(DRIFT)	-3.2		3.2	% FS	IP = IP(MAX), TA = -40°C to 125°C	10
Sensitivity Error Including Lifetime Drift	ESENS(DRIFT)	-3.8		3.8	%	IP = IP(MAX), TA = -40°C to 125°C	10
Offset Voltage Error Including Lifetime Drift	VOE(DRIFT)	-35		35	mV	IP = 0 A, TA = -40°C to 125°C	10
Sensitivity	S		100		mV/A	IRANGE(MIN) < IP < IRANGE(MAX)	10
Bandwidth	fBW		1		MHz	Small Signal = -3 dB	10
Noise	eN		9.5		mARMS	TA = 25°C, fBW = 100 kHz	10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		CCC pins be connected to as much copper area as possible. It is	22

CAD (KiCad official)

Symbol: CT417-HSN820DR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ct417-hsn820dr-etched.step / ct417-hsn820dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ct417-hsn820dr.step / ct417-hsn820dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (27 pp, sha256 b2fcdb1ea5c594ce, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CT417-HSN820DR

Verified CT417-HSN820DR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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