# CSD87334Q3D

**Texas Instruments** · MOSFETs · HVSON-8-EP(3x3)

CSD87334Q3D from Texas Instruments, in a HVSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power block input supply (control FET drain), rated up to 24 V recommended and 30 V absolute maximum to PGND, with ceramic input capacitors placed as close as possible to VIN and PGND. |
| 2 | VIN | power_in | Power block input supply (control FET drain), rated up to 24 V recommended and 30 V absolute maximum to PGND, with ceramic input capacitors placed as close as possible to VIN and PGND. |
| 3 | TG | input | Control FET gate, connected to the high-side output of the driver IC, with TG to TGR limited to -0.3 V to 10 V absolute maximum. |
| 4 | TGR | passive | Return path of the high-side gate drive, connected to the driver IC phase pin (LL/SW) together with the bootstrap capacitor. |
| 5 | BG | input | Sync FET gate, connected to the low-side output of the driver IC, with BG to PGND limited to -0.3 V to 10 V absolute maximum. |
| 6 | VSW | passive | Switching node of the half-bridge connected to the output inductor, rated 30 V to PGND (32 V for 10 ns) absolute maximum. |
| 7 | VSW | passive | Switching node of the half-bridge connected to the output inductor, rated 30 V to PGND (32 V for 10 ns) absolute maximum. |
| 8 | VSW | passive | Switching node of the half-bridge connected to the output inductor, rated 30 V to PGND (32 V for 10 ns) absolute maximum. |
| 9 | PGND | power_in | Power ground and exposed thermal pad (sync FET source) that must be soldered to the board as the primary thermal path, with RθJC of 2.1 °C/W via the PGND pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSON-8-EP(3x3) |
| Category | Triode/MOS Tube/Transistor |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage VIN to PGND |  |  |  | 30 | V |  | 3 |
| Voltage VSW to PGND |  |  |  | 30 | V |  | 3 |
| Voltage VSW to PGND (10 ns) |  |  |  | 32 | V | 10 ns | 3 |
| Voltage TG to TGR |  | -0.3 |  | 10 | V |  | 3 |
| Voltage BG to PGND |  | -0.3 |  | 10 | V |  | 3 |
| Pulsed current rating | IDM |  |  | 60 | A |  | 3 |
| Power dissipation | PD |  |  | 6 | W |  | 3 |
| Avalanche energy Sync FET | EAS |  |  | 48 | mJ | ID = 31 A, L = 0.1 mH | 3 |
| Avalanche energy Control FET | EAS |  |  | 48 | mJ | ID = 31 A, L = 0.1 mH | 3 |
| Operating junction temperature | TJ | -55 |  | 150 | °C |  | 3 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 3 |
| Gate drive voltage | VGS | 3.3 |  | 8 | V |  | 3 |
| Input supply voltage | VIN |  |  | 24 | V |  | 3 |
| Switching frequency | ƒSW |  |  | 1500 | kHz | CBST = 0.1 µF (min) | 3 |
| Operating current |  |  |  | 20 | A |  | 3 |
| Operating temperature | TJ |  |  | 125 | °C |  | 3 |
| Junction-to-ambient thermal resistance (min Cu) | RθJA |  |  | 130 | °C/W | min Cu | 3 |
| Junction-to-ambient thermal resistance (max Cu) | RθJA |  |  | 75 | °C/W | max Cu, 1 in² of 2-oz Cu | 3 |
| Junction-to-case thermal resistance (top of package) | RθJC |  | 21 |  | °C/W | top of package | 3 |
| Junction-to-case thermal resistance (PGND pin) | RθJC |  | 2.1 |  | °C/W | PGND pin | 3 |
| Power loss | PLOSS |  | 1.6 |  | W | VIN = 12 V, VGS = 5 V, VOUT = 3.3 V, IOUT = 12 A, ƒSW = 500 kHz, LOUT = 1 µH, TJ = 25°C | 3 |
| VIN quiescent current | IQVIN |  | 10 |  | µA | TG to TGR = 0 V, BG to PGND = 0 V | 3 |
| Drain-to-source voltage (Q1 control FET and Q2 sync FET) | BVDSS | 30 |  |  | V | VGS = 0 V, IDS = 250 µA | 4 |
| Drain-to-source leakage current (Q1 and Q2) | IDSS |  | 1 | 1 | µA | VGS = 0 V, VDS = 20 V | 4 |
| Gate-to-source leakage current (Q1 and Q2) | IGSS |  | 100 | 100 | nA | VDS = 0 V, VGS = 10 V | 4 |
| Gate-to-source threshold voltage (Q1 and Q2) | VGS(th) | 0.75 | 0.9 | 1.2 | V | VDS = VGS, IDS = 250 µA | 4 |
| Drain-to-source on resistance (Q1 and Q2) | RDS(on) |  | 6.3 | 8.3 | mΩ | VGS = 3.5 V, IDS = 12 A | 4 |
| Drain-to-source on resistance (Q1 and Q2) | RDS(on) |  | 5.6 | 7 | mΩ | VGS = 4.5 V, IDS = 12 A | 4 |
| Drain-to-source on resistance (Q1 and Q2) | RDS(on) |  | 4.9 | 6 | mΩ | VGS = 8 V, IDS = 12 A | 4 |
| Input capacitance (Q1 and Q2) | CISS |  | 971 | 1260 | pF | VGS = 0 V, VDS = 15 V, ƒ = 1 MHz | 4 |
| Output capacitance (Q1 and Q2) | COSS |  | 453 | 589 | pF | VGS = 0 V, VDS = 15 V, ƒ = 1 MHz | 4 |
| Reverse transfer capacitance (Q1 and Q2) | CRSS |  | 16 | 21 | pF | VGS = 0 V, VDS = 15 V, ƒ = 1 MHz | 4 |
| Series gate resistance (Q1 and Q2) | RG |  | 1 | 2 | Ω |  | 4 |
| Gate charge total (Q1 and Q2, 4.5 V) | Qg |  | 6.4 | 8.3 | nC | VDS = 15 V, IDS = 12 A | 4 |
| Diode forward voltage (Q1 and Q2) | VSD |  | 0.8 | 1 | V | IDS = 12 A, VGS = 0 V | 4 |

## CAD (KiCad official)

- Symbol: `CSD87334Q3D`
- Footprint: `Package_SON:HVSON-8-1EP_3x3mm_P0.65mm_EP1.6x2.4mm`
- 3D model: HVSON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `csd87334q3d-etched.step` / `csd87334q3d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `csd87334q3d.step` / `csd87334q3d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/csd87334q3d.pdf) (25 pp, sha256 `e69c399a73d40d51`, retrieved 2026-11-07, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/csd87334q3d-datasheet.pdf)