CS8416-CSZR

@@ -8,34 +8,34 @@ CS8416-CSZR from Cirrus Logic, in a SOIC-28. Pinout and pin descriptions extract  | Pin | Name | Type | Function | |---|---|---|---|-| 1 | RXP3 | input | Positive AES3/S/PDIF input 3, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND. |-| 2 | RXP2 | input | Positive AES3/S/PDIF input 2, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND. |-| 3 | RXP1 | input | Positive AES3/S/PDIF input 1, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND. |-| 4 | RXP0 | input | Positive AES3/S/PDIF input 0, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND. |-| 5 | RXN | input | Negative AES3/S/PDIF input used with RXP[7:0] to form a differential input; in single-ended operation AC couple it to ground through a capacitor. |-| 6 | VA | power_in | Analog power supply, nominally +3.3 V (3.13 V to 3.46 V); noise on this pin directly affects recovered clock jitter. |-| 7 | AGND | power_in | Analog ground; AGND and DGND should be connected to a common ground area under the chip. |-| 8 | FILT | passive | PLL loop filter pin; connect an RC network between this pin and analog ground, returning the filter ground end directly to AGND. |-| 9 | RST | input | Active-low reset; when low the device enters low power mode and resets all internal states, and must be held low at power-up until supplies and input clocks are stable. |-| 10 | RXP4 | input | Positive AES3/S/PDIF input 4 in Software Mode (RXSEL1 receiver MUX select in Hardware Mode). |-| 11 | RXP5 | input | Positive AES3/S/PDIF input 5 in Software Mode (RXSEL0 receiver MUX select in Hardware Mode). |-| 12 | RXP6 | input | Positive AES3/S/PDIF input 6 in Software Mode (TXSEL1 TX pass-through select in Hardware Mode). |-| 13 | RXP7 | input | Positive AES3/S/PDIF input 7 in Software Mode (TXSEL0 TX pass-through select in Hardware Mode). |-| 14 | AD0/CS | input | I²C address bit 0 or SPI chip select; a falling edge puts the control port into SPI mode, otherwise it defaults to I²C (NV/RERR output in Hardware Mode). |-| 15 | AD1/CDIN | input | I²C address bit 1 or SPI serial control data input (AUDIO output in Hardware Mode). |-| 16 | SCL/CCLK | input | Control port clock used to clock control data into and out of the device; requires an external pull-up resistor to VL (96KHZ output in Hardware Mode). |-| 17 | SDA/CDOUT | bidirectional | I²C open-drain control data I/O requiring a pull-up to VL, or SPI control port data output (RCBL output in Hardware Mode). |-| 18 | AD2/GPO2 | output | General purpose output 2; with the I²C control port this pin must be pulled high or low through a 47 kΩ resistor (U output in Hardware Mode). |-| 19 | GPO1 | output | General purpose output 1, routable to selected internal signals (C output in Hardware Mode). |-| 20 | GPO0 | output | General purpose output 0, routable to selected internal signals (TX pass-through output in Hardware Mode). |-| 21 | VL | power_in | Logic input/output power supply, nominally +3.3 V or +5.0 V (3.13 V to 5.25 V). |-| 22 | DGND | power_in | Digital and I/O ground; AGND and DGND should be connected to a common ground area under the chip. |-| 23 | VD | power_in | Digital core power supply, nominally +3.3 V (3.13 V to 3.46 V). |-| 24 | RMCK | output | Recovered master clock output from the PLL, 256x Fs by default or 128x Fs via RMCKF, and can be set to high impedance via RXD. |-| 25 | OMCK | input | System clock input that is automatically output on RMCK on PLL unlock when OMCK System Clock Mode is enabled. |-| 26 | SDOUT | output | Serial audio data output; must be pulled high to VL through a 47 kΩ resistor for Software Mode (pulled low to DGND for Hardware Mode). |-| 27 | OSCLK | bidirectional | Serial audio output bit clock for the SDOUT data, input or output depending on master/slave mode. |-| 28 | OLRCK | bidirectional | Serial audio output left/right word clock at the output sample rate Fs, input or output depending on master/slave mode. |+| 1 | RXP3 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 2 | RXP2 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 3 | RXP1 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 4 | RXP0 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 5 | RXN | input | Negative AES3/S/PDIF input forming a differential pair with RXP[7:0]; in single-ended operation it should be AC-coupled to ground through a capacitor. |+| 6 | VA | power_in | Analog power supply, nominally +3.3 V; noise on this pin directly affects the jitter performance of the recovered clock. |+| 7 | AGND | power_in | Ground for the analog circuitry; AGND and DGND should be connected to a common ground area under the chip. |+| 8 | FILT | output | PLL loop filter connection; an RC network connects between this pin and analog ground, with the ground end returned directly to AGND for minimum PLL jitter. |+| 9 | RST | input | Reset; when low the device enters a low-power mode and all internal states are reset, and RST must be held low at initial power-up until the supply and input clocks are stable. |+| 10 | RXP4 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 11 | RXP5 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 12 | RXP6 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 13 | RXP7 | input | Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND. |+| 14 | AD0 / CS | input | In I²C mode this is chip address bit 0; in SPI mode it is the chip select, and a falling edge on this pin selects SPI control port mode (otherwise I²C is the default). |+| 15 | AD1 / CDIN | input | In I²C mode this is chip address bit 1; in SPI mode it is the serial control data input. |+| 16 | SCL / CCLK | input | Control port clock used to clock control data bits into and out of the device; it is an open-drain line that requires an external pull-up to VL. |+| 17 | SDA / CDOUT | bidirectional | In I²C mode this is the open-drain control data I/O requiring an external pull-up to VL; in SPI mode it is the control data output (CDOUT). |+| 18 | AD2 / GPO2 | output | General-purpose output 2; when using the I²C control port this pin must be pulled high or low through a 47 kΩ resistor. |+| 19 | GPO1 | output | General-purpose output 1, with function selected through the GPO1SEL bits and defaulting to GND after reset. |+| 20 | GPO0 | output | General-purpose output 0, with function selected through the GPO0SEL bits and defaulting to GND after reset. |+| 21 | VL | power_in | Logic power supply for the input/output pins, nominally +3.3 V or +5.0 V. |+| 22 | DGND | power_in | Digital and I/O ground for the I/O and core logic; AGND and DGND should be connected to a common ground area under the chip. |+| 23 | VD | power_in | Digital core power supply, nominally +3.3 V. |+| 24 | RMCK | output | Input-section recovered master clock output from the PLL, at 256×Fs by default or 128×Fs when RMCKF is set, and may be set to high impedance through the RXD bit. |+| 25 | OMCK | input | System clock input; when OMCK System Clock Mode is enabled through the SWCLK bit it is output on RMCK upon PLL unlock and serves as the reference for the OMCK/RMCK ratio in register 18h. |+| 26 | SDOUT | output | Serial audio output data; this pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode. |+| 27 | OSCLK | bidirectional | Serial audio output bit clock for the SDOUT data, operating as an input or output depending on the serial port mode. |+| 28 | OLRCK | bidirectional | Serial audio output left/right word clock for the SDOUT data, whose frequency is the output sample rate Fs. |  ## Key specifications @@ -52,63 +52,57 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries  | Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page | |---|---|---|---|---|---|---|---|-| Power Supply Voltage VA | VA | 3.13 | 3.3 | 3.46 | V |  | 6 |-| Power Supply Voltage VD | VD | 3.13 | 3.3 | 3.46 | V |  | 6 |-| Power Supply Voltage VL | VL | 3.13 |  | 5.25 | V | typ printed as 3.3 or 5.0 | 6 |-| Ambient Operating Temperature, Commercial Grade | TA | -10 |  | 70 | °C | Commercial Grade | 6 |-| Power Supply Voltage (absolute max) | VA, VD, VL |  |  | 6 | V |  | 6 |-| Input Current, Any Pin Except Supplies | Iin | -10 |  | 10 | mA | Note 1: transient currents up to 100 mA will not cause SCR latch-up | 6 |-| Input Voltage | Vin | -0.3 |  |  | V | max printed as (VL) + 0.3 | 6 |-| Ambient Operating Temperature (power applied) | TA | -55 |  | 125 | °C |  | 6 |+| Power Supply Voltage (VA) | VA | 3.13 | 3.3 | 3.46 | V |  | 6 |+| Power Supply Voltage (VD) | VD | 3.13 | 3.3 | 3.46 | V |  | 6 |+| Power Supply Voltage (VL) | VL | 3.13 |  | 5.25 | V |  | 6 |+| Ambient Operating Temperature, Commercial Grade | TA | -10 |  | 70 | °C |  | 6 |+| Power Supply Voltage (VA, VD, VL) |  |  |  | 6 | V |  | 6 |+| Input Current, Any Pin Except Supplies | Iin | -10 |  | 10 | mA | Any pin except supplies (Note 1) | 6 |+| Input Voltage | Vin | -0.3 |  |  | V |  | 6 |+| Ambient Operating Temperature (power applied) | TA | -55 |  | 125 | °C | Power applied | 6 | | Storage Temperature | Tstg | -65 |  | 150 | °C |  | 6 | | Input Leakage Current | IIN | -0.5 |  | 0.5 | μA |  | 7 |-| Differential Input Sensitivity, RXP[7:0] to RXN | VTH |  | 150 | 200 | mVpp |  | 7 |+| Differential Input Sensitivity, RXP[7:0] to RXN | VTH |  | 150 | 200 | mVpp | RXP[7:0] to RXN | 7 | | Input Hysteresis | VH | 0.15 |  | 1 | V |  | 7 | | Low-Level Output Voltage | VOL |  |  | 0.5 | V | IOL = 3.2 mA | 7 |-| High-Level Input Voltage | VIH | 2 |  |  | V | except RXP[7:0], RXN; max printed as (VL) + 0.3 | 7 |-| Low-Level Input Voltage | VIL | -0.3 |  | 0.8 | V | except RXP[7:0], RXN | 7 |+| High-Level Input Voltage, except RXP[7:0], RXN | VIH | 2 |  |  | V | Except RXP[7:0], RXN | 7 |+| Low-Level Input Voltage, except RXP[7:0], RXN | VIL | -0.3 |  | 0.8 | V | Except RXP[7:0], RXN | 7 | | RST Pin Low Pulse Width |  | 200 |  |  | μS |  | 8 | | PLL Clock Recovery Sample Rate Range |  | 30 |  | 200 | kHz |  | 8 |-| RMCK Output Duty-Cycle (recovered from biphase input) |  | 45 | 50 | 55 | % | Note 6 | 8 |-| RMCK Output Duty-Cycle (OMCK switched over) |  | 55 |  | 65 | % | Note 7; columns printed as 50 / 55 / 65 with min 45 for Note 6 | 8 |+| RMCK Output Duty-Cycle |  | 45 |  | 55 | % | Note 6: clock recovered from biphase encoded input | 8 |+| RMCK Output Duty-Cycle |  | 50 |  | 65 | % | Note 7: OMCK switched over for output on RMCK | 8 | | RMCK/OMCK Maximum Frequency |  |  |  | 50 | MHz |  | 8 | | OSCLK/OLRCK Active Edge to SDOUT Output Valid | tdpd |  |  | 23 | ns | Note 8 | 9 |-| RMCK to OSCLK active edge delay | tsmd | 0 |  | 12 | ns | Master Mode, Note 8 | 9 |-| RMCK to OLRCK delay | tlmd | 0 |  | 12 | ns | Master Mode, Note 9 | 9 |-| OSCLK Period | tsckw | 36 |  |  | ns | Slave Mode | 9 |-| OSCLK Input Low Width | tsckl | 14 |  |  | ns | Slave Mode | 9 |-| OSCLK Input High Width | tsckh | 14 |  |  | ns | Slave Mode | 9 |-| OSCLK Active Edge to OLRCK Edge | tlrckd | 10 |  |  | ns | Slave Mode, Notes 8,9,10 | 9 |-| OSCLK Edge Setup Before OSCLK Active-Edge | tlrcks | 10 |  |  | ns | Slave Mode, Notes 8,9,11 | 9 |-| CCLK Clock Frequency | fsck | 0 |  | 6 | MHz | SPI mode, Note 12 | 10 |-| CS High Time Between Transmissions | tcsh | 1 |  |  | µs | SPI mode | 10 |-| CS Falling to CCLK Edge | tcss | 20 |  |  | ns | SPI mode | 10 |-| CCLK Low Time | tscl | 66 |  |  | ns | SPI mode | 10 |-| CCLK High Time | tsch | 66 |  |  | ns | SPI mode | 10 |-| CDIN to CCLK Rising Setup Time | tdsu | 40 |  |  | ns | SPI mode | 10 |-| CCLK Rising to DATA Hold Time | tdh | 15 |  |  | ns | SPI mode, Note 13 | 10 |-| CCLK Falling to CDOUT Stable | tpd |  |  | 50 | ns | SPI mode | 10 |-| Rise Time of CDOUT | tr1 |  |  | 25 | ns | SPI mode | 10 |-| Fall Time of CDOUT | tf1 |  |  | 25 | ns | SPI mode | 10 |-| Rise Time of CCLK and CDIN | tr2 |  |  | 100 | ns | SPI mode, Note 14 | 10 |-| Fall Time of CCLK and CDIN | tr2 |  |  | 100 | ns | SPI mode, Note 14 | 10 |-| SCL Clock Frequency | fscl |  |  | 100 | kHz | I²C | 11 |-| Bus Free Time Between Transmissions | tbuf | 4.7 |  |  | µs | I²C | 11 |-| Start Condition Hold Time | thdst | 4 |  |  | µs | I²C, prior to first clock pulse | 11 |-| Clock Low time | tlow | 4.7 |  |  | µs | I²C | 11 |-| Clock High Time | thigh | 4 |  |  | µs | I²C | 11 |-| Setup Time for Repeated Start Condition | tsust | 4.7 |  |  | µs | I²C | 11 |-| SDA Hold Time from SCL Falling | thdd | 10 |  |  | ns | I²C, Note 15 | 11 |-| SDA Setup time to SCL Rising | tsud | 250 |  |  | ns | I²C | 11 |-| Rise Time of SCL and SDA | tr |  |  | 1000 | ns | I²C | 11 |-| Fall Time SCL and SDA | tf |  |  | 300 | ns | I²C | 11 |-| Setup Time for Stop Condition | tsusp | 4.7 |  |  | µs | I²C | 11 |-| Supply Current in power-down, VA | IA |  | 10 |  | μA | Power-Down Mode, Notes 2, 4 | 7 |-| Supply Current in power-down, VD | ID |  | 70 |  | μA | Power-Down Mode, Notes 2, 4 | 7 |-| Supply Current at 48 kHz frame rate, VA | IA |  | 5.7 |  | mA | Normal Operation, Notes 3, 4 | 7 |-| Supply Current at 48 kHz frame rate, VD | ID |  | 5.9 |  | mA | Normal Operation, Notes 3, 4 | 7 |-| Supply Current at 192 kHz frame rate, VA | IA |  | 9.4 |  | mA | Normal Operation, Notes 3, 4 | 7 |-| Supply Current at 192 kHz frame rate, VD | ID |  | 23 |  | mA | Normal Operation, Notes 3, 4 | 7 |+| RMCK to OSCLK Active Edge Delay (Master Mode) | tsmd | 0 |  | 12 | ns | Note 8 | 9 |+| RMCK to OLRCK Delay (Master Mode) | tlmd | 0 |  | 12 | ns | Note 9 | 9 |+| OSCLK Period (Slave Mode) | tsckw | 36 |  |  | ns |  | 9 |+| OSCLK Input Low Width (Slave Mode) | tsckl | 14 |  |  | ns |  | 9 |+| OSCLK Input High Width (Slave Mode) | tsckh | 14 |  |  | ns |  | 9 |+| OSCLK Active Edge to OLRCK Edge (Slave Mode) | tlrckd | 10 |  |  | ns | Notes 8, 9, 10 | 9 |+| OSCLK Edge Setup Before OSCLK Active-Edge (Slave Mode) | tlrcks | 10 |  |  | ns | Notes 8, 9, 11 | 9 |+| CCLK Clock Frequency | fsck | 0 |  | 6 | MHz | See Note 12: if Fs < 46.875 kHz, CCLK < 128 Fs | 10 |+| CS High Time Between Transmissions | tcsh | 1 |  |  | µs |  | 10 |+| CS Falling to CCLK Edge | tcss | 20 |  |  | ns |  | 10 |+| CCLK Low Time | tscl | 66 |  |  | ns |  | 10 |+| CCLK High Time | tsch | 66 |  |  | ns |  | 10 |+| CDIN to CCLK Rising Setup Time | tdsu | 40 |  |  | ns |  | 10 |+| CCLK Rising to DATA Hold Time | tdh | 15 |  |  | ns | Note 13: data held to bridge CCLK transition time | 10 |+| CCLK Falling to CDOUT Stable | tpd |  |  | 50 | ns |  | 10 |+| Rise Time of CDOUT | tr1 |  |  | 25 | ns |  | 10 |+| Fall Time of CDOUT | tf1 |  |  | 25 | ns |  | 10 |+| Rise Time of CCLK and CDIN | tr2 |  |  | 100 | ns | Note 14: for fsck < 1 MHz | 10 |+| Fall Time of CCLK and CDIN | tr2 |  |  | 100 | ns | Note 14: for fsck < 1 MHz | 10 |+| SCL Clock Frequency | fscl |  |  | 100 | kHz |  | 11 |+| Bus Free Time Between Transmissions | tbuf | 4.7 |  |  | µs |  | 11 |+| Start Condition Hold Time (prior to first clock pulse) | thdst | 4 |  |  | µs |  | 11 |+| Clock Low Time | tlow | 4.7 |  |  | µs |  | 11 |+| Clock High Time | thigh | 4 |  |  | µs |  | 11 |+| Setup Time for Repeated Start Condition | tsust | 4.7 |  |  | µs |  | 11 |+| SDA Hold Time from SCL Falling | thdd | 10 |  |  | ns | Note 15: 300 ns SCL transition time | 11 |+| SDA Setup Time to SCL Rising | tsud | 250 |  |  | ns |  | 11 |+| Rise Time of SCL and SDA | tr |  |  | 1000 | ns |  | 11 |+| Fall Time SCL and SDA | tf |  |  | 300 | ns |  | 11 |+| Setup Time for Stop Condition | tsusp | 4.7 |  |  | µs |  | 11 |  ## CAD (KiCad official) @@ -122,7 +116,7 @@ Limits as printed in the datasheet (page.json `metadata.characteristics` carries Data extracted from the manufacturer datasheet, not a distributor listing:  - **Datasheet:** [Cirrus Logic datasheet](docs/cs8416-cszr-datasheet.pdf) (60 pp, sha256 `85bb158d11c6e9bf`, retrieved 2026-11-12, tier: lcsc)-- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - **CAD:** KiCad official libraries (CC-BY-SA 4.0).  [Datasheet PDF](docs/cs8416-cszr-datasheet.pdf)

@@ -1,6 +1,6 @@ {   "slug": "cs8416-cszr",-  "version": "0.1.0",+  "version": "0.1.1",   "type": "component",   "description": "Cirrus Logic Audio Interface ICs, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",   "tags": [@@ -54,7 +54,7 @@       "mouser": "777-CS8416-CSZR"     },     "distributor_check": {-      "checked_at": "2026-11-12T04:55:49Z",+      "checked_at": "2026-11-12T07:57:37Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": "598-CS8416-CSZRTR-ND",@@ -70,169 +70,169 @@         "number": "1",         "name": "RXP3",         "type": "input",-        "description": "Positive AES3/S/PDIF input 3, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "2",         "name": "RXP2",         "type": "input",-        "description": "Positive AES3/S/PDIF input 2, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "3",         "name": "RXP1",         "type": "input",-        "description": "Positive AES3/S/PDIF input 1, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "4",         "name": "RXP0",         "type": "input",-        "description": "Positive AES3/S/PDIF input 0, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "5",         "name": "RXN",         "type": "input",-        "description": "Negative AES3/S/PDIF input used with RXP[7:0] to form a differential input; in single-ended operation AC couple it to ground through a capacitor."+        "description": "Negative AES3/S/PDIF input forming a differential pair with RXP[7:0]; in single-ended operation it should be AC-coupled to ground through a capacitor."       },       {         "number": "6",         "name": "VA",         "type": "power_in",-        "description": "Analog power supply, nominally +3.3 V (3.13 V to 3.46 V); noise on this pin directly affects recovered clock jitter."+        "description": "Analog power supply, nominally +3.3 V; noise on this pin directly affects the jitter performance of the recovered clock."       },       {         "number": "7",         "name": "AGND",         "type": "power_in",-        "description": "Analog ground; AGND and DGND should be connected to a common ground area under the chip."+        "description": "Ground for the analog circuitry; AGND and DGND should be connected to a common ground area under the chip."       },       {         "number": "8",         "name": "FILT",-        "type": "passive",-        "description": "PLL loop filter pin; connect an RC network between this pin and analog ground, returning the filter ground end directly to AGND."+        "type": "output",+        "description": "PLL loop filter connection; an RC network connects between this pin and analog ground, with the ground end returned directly to AGND for minimum PLL jitter."       },       {         "number": "9",         "name": "RST",         "type": "input",-        "description": "Active-low reset; when low the device enters low power mode and resets all internal states, and must be held low at power-up until supplies and input clocks are stable."+        "description": "Reset; when low the device enters a low-power mode and all internal states are reset, and RST must be held low at initial power-up until the supply and input clocks are stable."       },       {         "number": "10",         "name": "RXP4",         "type": "input",-        "description": "Positive AES3/S/PDIF input 4 in Software Mode (RXSEL1 receiver MUX select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "11",         "name": "RXP5",         "type": "input",-        "description": "Positive AES3/S/PDIF input 5 in Software Mode (RXSEL0 receiver MUX select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "12",         "name": "RXP6",         "type": "input",-        "description": "Positive AES3/S/PDIF input 6 in Software Mode (TXSEL1 TX pass-through select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "13",         "name": "RXP7",         "type": "input",-        "description": "Positive AES3/S/PDIF input 7 in Software Mode (TXSEL0 TX pass-through select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "14",-        "name": "AD0/CS",+        "name": "AD0 / CS",         "type": "input",-        "description": "I²C address bit 0 or SPI chip select; a falling edge puts the control port into SPI mode, otherwise it defaults to I²C (NV/RERR output in Hardware Mode)."+        "description": "In I²C mode this is chip address bit 0; in SPI mode it is the chip select, and a falling edge on this pin selects SPI control port mode (otherwise I²C is the default)."       },       {         "number": "15",-        "name": "AD1/CDIN",+        "name": "AD1 / CDIN",         "type": "input",-        "description": "I²C address bit 1 or SPI serial control data input (AUDIO output in Hardware Mode)."+        "description": "In I²C mode this is chip address bit 1; in SPI mode it is the serial control data input."       },       {         "number": "16",-        "name": "SCL/CCLK",+        "name": "SCL / CCLK",         "type": "input",-        "description": "Control port clock used to clock control data into and out of the device; requires an external pull-up resistor to VL (96KHZ output in Hardware Mode)."+        "description": "Control port clock used to clock control data bits into and out of the device; it is an open-drain line that requires an external pull-up to VL."       },       {         "number": "17",-        "name": "SDA/CDOUT",+        "name": "SDA / CDOUT",         "type": "bidirectional",-        "description": "I²C open-drain control data I/O requiring a pull-up to VL, or SPI control port data output (RCBL output in Hardware Mode)."+        "description": "In I²C mode this is the open-drain control data I/O requiring an external pull-up to VL; in SPI mode it is the control data output (CDOUT)."       },       {         "number": "18",-        "name": "AD2/GPO2",+        "name": "AD2 / GPO2",         "type": "output",-        "description": "General purpose output 2; with the I²C control port this pin must be pulled high or low through a 47 kΩ resistor (U output in Hardware Mode)."+        "description": "General-purpose output 2; when using the I²C control port this pin must be pulled high or low through a 47 kΩ resistor."       },       {         "number": "19",         "name": "GPO1",         "type": "output",-        "description": "General purpose output 1, routable to selected internal signals (C output in Hardware Mode)."+        "description": "General-purpose output 1, with function selected through the GPO1SEL bits and defaulting to GND after reset."       },       {         "number": "20",         "name": "GPO0",         "type": "output",-        "description": "General purpose output 0, routable to selected internal signals (TX pass-through output in Hardware Mode)."+        "description": "General-purpose output 0, with function selected through the GPO0SEL bits and defaulting to GND after reset."       },       {         "number": "21",         "name": "VL",         "type": "power_in",-        "description": "Logic input/output power supply, nominally +3.3 V or +5.0 V (3.13 V to 5.25 V)."+        "description": "Logic power supply for the input/output pins, nominally +3.3 V or +5.0 V."       },       {         "number": "22",         "name": "DGND",         "type": "power_in",-        "description": "Digital and I/O ground; AGND and DGND should be connected to a common ground area under the chip."+        "description": "Digital and I/O ground for the I/O and core logic; AGND and DGND should be connected to a common ground area under the chip."       },       {         "number": "23",         "name": "VD",         "type": "power_in",-        "description": "Digital core power supply, nominally +3.3 V (3.13 V to 3.46 V)."+        "description": "Digital core power supply, nominally +3.3 V."       },       {         "number": "24",         "name": "RMCK",         "type": "output",-        "description": "Recovered master clock output from the PLL, 256x Fs by default or 128x Fs via RMCKF, and can be set to high impedance via RXD."+        "description": "Input-section recovered master clock output from the PLL, at 256×Fs by default or 128×Fs when RMCKF is set, and may be set to high impedance through the RXD bit."       },       {         "number": "25",         "name": "OMCK",         "type": "input",-        "description": "System clock input that is automatically output on RMCK on PLL unlock when OMCK System Clock Mode is enabled."+        "description": "System clock input; when OMCK System Clock Mode is enabled through the SWCLK bit it is output on RMCK upon PLL unlock and serves as the reference for the OMCK/RMCK ratio in register 18h."       },       {         "number": "26",         "name": "SDOUT",         "type": "output",-        "description": "Serial audio data output; must be pulled high to VL through a 47 kΩ resistor for Software Mode (pulled low to DGND for Hardware Mode)."+        "description": "Serial audio output data; this pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode."       },       {         "number": "27",         "name": "OSCLK",         "type": "bidirectional",-        "description": "Serial audio output bit clock for the SDOUT data, input or output depending on master/slave mode."+        "description": "Serial audio output bit clock for the SDOUT data, operating as an input or output depending on the serial port mode."       },       {         "number": "28",         "name": "OLRCK",         "type": "bidirectional",-        "description": "Serial audio output left/right word clock at the output sample rate Fs, input or output depending on master/slave mode."+        "description": "Serial audio output left/right word clock for the SDOUT data, whose frequency is the output sample rate Fs."       }     ],     "provenance": {@@ -240,17 +240,17 @@       "factory_chain": {         "factory": "2.0.0",         "extractor": "extract_pins 0.3",-        "primary_model": "claude-sonnet-5-5",+        "primary_model": "claude-haiku-5-5",         "primary_mode": "text",         "consensus_model": "claude-sonnet-5-5",         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: CS8416-CSZR is the 28-SOIC tape-and-reel part (ordering table, page 59). The datasheet gives one sha; Pins 10-20 change function between Software Mode and Hardware Mode, selected by SDOUT pull-up or pul; FILT is described as 'PLL Loop Filter (Output)' but connects to an external RC network, so it is typ"+          "extractor flagged: Pinout given is the Software Mode description (datasheet section 2.1, SOIC/TSSOP share the same numb; FILT is typed 'output' as the datasheet labels it, but it is an RC filter node rather than a driven ; SCL/CCLK is labelled '(Input)' in the datasheet but the text also says CCLK is an open-drain output;"         ],         "pages_sent": 27,-        "cost_usd": 0.2815,-        "at": "2026-11-12T04:55:26"+        "cost_usd": 0.1534,+        "at": "2026-11-12T07:56:57"       },       "datasheet": {         "url": "https://datasheet.lcsc.com/datasheet/pdf/8f2da87ad1926efe8d911b810a837856.pdf",@@ -305,13 +305,13 @@         "zmin_mm": -0.0,         "centre_offset_mm": 0.0,         "footprint_binding": "identity",-        "sha256": "a4257deef52f3c43b65c45342fe26b8e434c3b1415090ab1e5357a56a349a6d9",+        "sha256": "285b1b680bdbb376c31520e326a5f1c0603dee11f3356b86c3afce25c365672b",         "checked": "2026-11-12",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ],     "package_dims": {-      "package_code": "28L SOIC (300 MIL BODY), JEDEC MS-013",+      "package_code": "28L SOIC (300 MIL BODY), MS-013",       "source_page": 56,       "D": {         "nom_mm": 17.9,

@@ -4,7 +4,7 @@   "slug": "cs8416-cszr",   "title": "CS8416-CSZR",   "brief": "Cirrus Logic Audio Interface ICs, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.1.1",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -36,7 +36,7 @@       "mouser": "777-CS8416-CSZR"     },     "distributor_check": {-      "checked_at": "2026-11-12T04:55:49Z",+      "checked_at": "2026-11-12T07:57:37Z",       "source": "Component Ocean /api/assign-pns",       "digikey": {         "pn": "598-CS8416-CSZRTR-ND",@@ -52,169 +52,169 @@         "number": "1",         "name": "RXP3",         "type": "input",-        "description": "Positive AES3/S/PDIF input 3, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "2",         "name": "RXP2",         "type": "input",-        "description": "Positive AES3/S/PDIF input 2, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "3",         "name": "RXP1",         "type": "input",-        "description": "Positive AES3/S/PDIF input 1, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "4",         "name": "RXP0",         "type": "input",-        "description": "Positive AES3/S/PDIF input 0, one of the RXP[7:0] 8:2 input multiplexer inputs in Software Mode; unused inputs should be left floating or tied to AGND."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "5",         "name": "RXN",         "type": "input",-        "description": "Negative AES3/S/PDIF input used with RXP[7:0] to form a differential input; in single-ended operation AC couple it to ground through a capacitor."+        "description": "Negative AES3/S/PDIF input forming a differential pair with RXP[7:0]; in single-ended operation it should be AC-coupled to ground through a capacitor."       },       {         "number": "6",         "name": "VA",         "type": "power_in",-        "description": "Analog power supply, nominally +3.3 V (3.13 V to 3.46 V); noise on this pin directly affects recovered clock jitter."+        "description": "Analog power supply, nominally +3.3 V; noise on this pin directly affects the jitter performance of the recovered clock."       },       {         "number": "7",         "name": "AGND",         "type": "power_in",-        "description": "Analog ground; AGND and DGND should be connected to a common ground area under the chip."+        "description": "Ground for the analog circuitry; AGND and DGND should be connected to a common ground area under the chip."       },       {         "number": "8",         "name": "FILT",-        "type": "passive",-        "description": "PLL loop filter pin; connect an RC network between this pin and analog ground, returning the filter ground end directly to AGND."+        "type": "output",+        "description": "PLL loop filter connection; an RC network connects between this pin and analog ground, with the ground end returned directly to AGND for minimum PLL jitter."       },       {         "number": "9",         "name": "RST",         "type": "input",-        "description": "Active-low reset; when low the device enters low power mode and resets all internal states, and must be held low at power-up until supplies and input clocks are stable."+        "description": "Reset; when low the device enters a low-power mode and all internal states are reset, and RST must be held low at initial power-up until the supply and input clocks are stable."       },       {         "number": "10",         "name": "RXP4",         "type": "input",-        "description": "Positive AES3/S/PDIF input 4 in Software Mode (RXSEL1 receiver MUX select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "11",         "name": "RXP5",         "type": "input",-        "description": "Positive AES3/S/PDIF input 5 in Software Mode (RXSEL0 receiver MUX select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "12",         "name": "RXP6",         "type": "input",-        "description": "Positive AES3/S/PDIF input 6 in Software Mode (TXSEL1 TX pass-through select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "13",         "name": "RXP7",         "type": "input",-        "description": "Positive AES3/S/PDIF input 7 in Software Mode (TXSEL0 TX pass-through select in Hardware Mode)."+        "description": "Positive AES3/S/PDIF input, single-ended or differential, part of the 8:2 S/PDIF input multiplexer; unused multiplexer inputs should be left floating or tied to AGND."       },       {         "number": "14",-        "name": "AD0/CS",+        "name": "AD0 / CS",         "type": "input",-        "description": "I²C address bit 0 or SPI chip select; a falling edge puts the control port into SPI mode, otherwise it defaults to I²C (NV/RERR output in Hardware Mode)."+        "description": "In I²C mode this is chip address bit 0; in SPI mode it is the chip select, and a falling edge on this pin selects SPI control port mode (otherwise I²C is the default)."       },       {         "number": "15",-        "name": "AD1/CDIN",+        "name": "AD1 / CDIN",         "type": "input",-        "description": "I²C address bit 1 or SPI serial control data input (AUDIO output in Hardware Mode)."+        "description": "In I²C mode this is chip address bit 1; in SPI mode it is the serial control data input."       },       {         "number": "16",-        "name": "SCL/CCLK",+        "name": "SCL / CCLK",         "type": "input",-        "description": "Control port clock used to clock control data into and out of the device; requires an external pull-up resistor to VL (96KHZ output in Hardware Mode)."+        "description": "Control port clock used to clock control data bits into and out of the device; it is an open-drain line that requires an external pull-up to VL."       },       {         "number": "17",-        "name": "SDA/CDOUT",+        "name": "SDA / CDOUT",         "type": "bidirectional",-        "description": "I²C open-drain control data I/O requiring a pull-up to VL, or SPI control port data output (RCBL output in Hardware Mode)."+        "description": "In I²C mode this is the open-drain control data I/O requiring an external pull-up to VL; in SPI mode it is the control data output (CDOUT)."       },       {         "number": "18",-        "name": "AD2/GPO2",+        "name": "AD2 / GPO2",         "type": "output",-        "description": "General purpose output 2; with the I²C control port this pin must be pulled high or low through a 47 kΩ resistor (U output in Hardware Mode)."+        "description": "General-purpose output 2; when using the I²C control port this pin must be pulled high or low through a 47 kΩ resistor."       },       {         "number": "19",         "name": "GPO1",         "type": "output",-        "description": "General purpose output 1, routable to selected internal signals (C output in Hardware Mode)."+        "description": "General-purpose output 1, with function selected through the GPO1SEL bits and defaulting to GND after reset."       },       {         "number": "20",         "name": "GPO0",         "type": "output",-        "description": "General purpose output 0, routable to selected internal signals (TX pass-through output in Hardware Mode)."+        "description": "General-purpose output 0, with function selected through the GPO0SEL bits and defaulting to GND after reset."       },       {         "number": "21",         "name": "VL",         "type": "power_in",-        "description": "Logic input/output power supply, nominally +3.3 V or +5.0 V (3.13 V to 5.25 V)."+        "description": "Logic power supply for the input/output pins, nominally +3.3 V or +5.0 V."       },       {         "number": "22",         "name": "DGND",         "type": "power_in",-        "description": "Digital and I/O ground; AGND and DGND should be connected to a common ground area under the chip."+        "description": "Digital and I/O ground for the I/O and core logic; AGND and DGND should be connected to a common ground area under the chip."       },       {         "number": "23",         "name": "VD",         "type": "power_in",-        "description": "Digital core power supply, nominally +3.3 V (3.13 V to 3.46 V)."+        "description": "Digital core power supply, nominally +3.3 V."       },       {         "number": "24",         "name": "RMCK",         "type": "output",-        "description": "Recovered master clock output from the PLL, 256x Fs by default or 128x Fs via RMCKF, and can be set to high impedance via RXD."+        "description": "Input-section recovered master clock output from the PLL, at 256×Fs by default or 128×Fs when RMCKF is set, and may be set to high impedance through the RXD bit."       },       {         "number": "25",         "name": "OMCK",         "type": "input",-        "description": "System clock input that is automatically output on RMCK on PLL unlock when OMCK System Clock Mode is enabled."+        "description": "System clock input; when OMCK System Clock Mode is enabled through the SWCLK bit it is output on RMCK upon PLL unlock and serves as the reference for the OMCK/RMCK ratio in register 18h."       },       {         "number": "26",         "name": "SDOUT",         "type": "output",-        "description": "Serial audio data output; must be pulled high to VL through a 47 kΩ resistor for Software Mode (pulled low to DGND for Hardware Mode)."+        "description": "Serial audio output data; this pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode."       },       {         "number": "27",         "name": "OSCLK",         "type": "bidirectional",-        "description": "Serial audio output bit clock for the SDOUT data, input or output depending on master/slave mode."+        "description": "Serial audio output bit clock for the SDOUT data, operating as an input or output depending on the serial port mode."       },       {         "number": "28",         "name": "OLRCK",         "type": "bidirectional",-        "description": "Serial audio output left/right word clock at the output sample rate Fs, input or output depending on master/slave mode."+        "description": "Serial audio output left/right word clock for the SDOUT data, whose frequency is the output sample rate Fs."       }     ],     "provenance": {@@ -222,17 +222,17 @@       "factory_chain": {         "factory": "2.0.0",         "extractor": "extract_pins 0.3",-        "primary_model": "claude-sonnet-5-5",+        "primary_model": "claude-haiku-5-5",         "primary_mode": "text",         "consensus_model": "claude-sonnet-5-5",         "consensus": "agreed",         "guards": "pin_guards 0.1: passed",         "guard_notes": [-          "extractor flagged: CS8416-CSZR is the 28-SOIC tape-and-reel part (ordering table, page 59). The datasheet gives one sha; Pins 10-20 change function between Software Mode and Hardware Mode, selected by SDOUT pull-up or pul; FILT is described as 'PLL Loop Filter (Output)' but connects to an external RC network, so it is typ"+          "extractor flagged: Pinout given is the Software Mode description (datasheet section 2.1, SOIC/TSSOP share the same numb; FILT is typed 'output' as the datasheet labels it, but it is an RC filter node rather than a driven ; SCL/CCLK is labelled '(Input)' in the datasheet but the text also says CCLK is an open-drain output;"         ],         "pages_sent": 27,-        "cost_usd": 0.2815,-        "at": "2026-11-12T04:55:26"+        "cost_usd": 0.1534,+        "at": "2026-11-12T07:56:57"       },       "datasheet": {         "url": "https://datasheet.lcsc.com/datasheet/pdf/8f2da87ad1926efe8d911b810a837856.pdf",@@ -287,13 +287,13 @@         "zmin_mm": 0,         "centre_offset_mm": 0,         "footprint_binding": "identity",-        "sha256": "a4257deef52f3c43b65c45342fe26b8e434c3b1415090ab1e5357a56a349a6d9",+        "sha256": "285b1b680bdbb376c31520e326a5f1c0603dee11f3356b86c3afce25c365672b",         "checked": "2026-11-12",         "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"       }     ],     "package_dims": {-      "package_code": "28L SOIC (300 MIL BODY), JEDEC MS-013",+      "package_code": "28L SOIC (300 MIL BODY), MS-013",       "source_page": 56,       "D": {         "nom_mm": 17.9,@@ -1079,5 +1079,7 @@   ],   "visibility": {     "public": true-  }+  },+  "description": "Cirrus Logic Audio Interface ICs, SOIC-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "org": "adom" }\ No newline at end of file