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CS5550-ISZ

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Cirrus Logic Analog To Digital Converters (ADCs), SSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS5550-ISZ

Cirrus Logic · Analog To Digital Converters (ADCs) · SSOP-24

CS5550-ISZ from Cirrus Logic, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XOUT output Crystal oscillator output; an internal gate connects to XIN/XOUT for a crystal to provide the system clock.
2 CPUCLK output Output of the on-chip oscillator which can drive one standard CMOS load.
3 VD+ power_in Positive digital supply relative to DGND.
4 DGND power_in Digital ground; its common-mode potential must be equal to or above the common-mode potential of AGND.
5 SCLK input Serial clock input that sets the data rate of SDI and SDO; recognized only when CS is low.
6 SDO tri_state Serial data port output, in a high impedance state when CS is high.
7 CS input Chip select; when low the port recognizes SCLK, when high SDO is forced to high impedance, and it should be changed only when SCLK is low.
8 TSTO unconnected Test output used for factory testing; must be left floating.
9 AIN2+ input Positive differential analog input of channel 2.
10 AIN2- input Negative differential analog input of channel 2.
11 VREFOUT output On-chip voltage reference output, nominally 2.5 V referenced to AGND.
12 VREFIN input Input that establishes the voltage reference for the on-chip modulator.
13 AGND power_in Analog ground; must be at the lowest potential.
14 VA+ power_in Positive analog supply relative to AGND.
15 AIN1- input Negative differential analog input of channel 1.
16 AIN1+ input Positive differential analog input of channel 1.
17 TSTO unconnected Test output used for factory testing; must be left floating.
18 TSTO unconnected Test output used for factory testing; must be left floating.
19 RESET input When taken low, all internal registers are set to their default states.
20 INT output Interrupt output; goes low to signal that an enabled event has occurred.
21 TSTO unconnected Test output used for factory testing; must be left floating.
22 TSTO unconnected Test output used for factory testing; must be left floating.
23 SDI input Serial data port input; data is input at a rate determined by SCLK.
24 XIN input Crystal input, or external CMOS-compatible clock input providing the system clock.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package SSOP-24
Category Data Converters
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 dB 5
AIN1 Differential Input Voltage Range AIN1 0 500 mVP-P Gain = 10 5
AIN1 Differential Input Voltage Range AIN1 0 100 mVP-P Gain = 50 5
Total Harmonic Distortion AIN1 THD1 80 dB 5
Common Mode + Signal AIN1 -0.25 V Both Gain Ranges; max printed as VA+ 5
Crosstalk with AIN2 at Full Scale -115 dB 50, 60 Hz 5
Effective Input Impedance AIN1 EII1 30 kΩ Gain = 10 5
Noise (Referred to Input) AIN1 N1 22.5 µVrms Gain = 10 5
Noise (Referred to Input) AIN1 N1 4.5 µVrms Gain = 50 5
Bipolar Offset Error AIN1 VOS -0.001 0.001 %F.S. After system calibration 5
Full-Scale Error AIN1 FSE -0.001 0.001 %F.S. After system calibration 5
AIN2 Differential Input Voltage Range AIN2 0 500 mVP-P 5
Total Harmonic Distortion AIN2 THD2 65 dB 5
Common Mode + Signal AIN2 -0.25 V max printed as VA+ 5
Crosstalk with AIN1 at Full Scale -70 dB 50, 60 Hz 5
Effective Input Impedance AIN2 EII2 5 MΩ Gain = 10 5
Noise (Referred to Input) AIN2 N2 150 µVrms Gain = 10 5
Bipolar Offset Error AIN2 VOS -0.01 0.01 %F.S. After system calibration 5
Full-Scale Error AIN2 FSE -0.01 0.01 %F.S. After system calibration 5
Full Scale Calibration Range FSCR 25 100 %F.S. 6
Power Consumption Active State PC 21 30 mW VD+ = 5 V, outputs unloaded, inputs CMOS level 6
Power Supply Rejection Ratio AIN1 PSRR1 56 dB Gain = 10, 50, 60 Hz 6
Power Supply Rejection Ratio AIN1 PSRR1 70 dB Gain = 50, 50, 60 Hz 6
Reference Output Voltage REFOUT 2.4 2.6 V 6
Reference Temperature Coefficient TC 25 60 ppm/°C 6
Reference Load Regulation ΔVR 6 10 mV Output Current 1 µA Source or Sink 6
Reference Input Voltage Range VREFIN 2.4 2.5 2.6 V 6
Low-Level Input Voltage (5 V), All Pins Except XIN, SCLK, RESET VIL 0.8 V 5 V digital 7
Low-Level Input Voltage (5 V), XIN VIL 1.5 V 5 V digital 7
Low-Level Input Voltage (3 V), All Pins Except XIN, SCLK, RESET VIL 0.48 V 3 V digital 7
Low-Level Input Voltage (3 V), XIN VIL 0.3 V 3 V digital 7
Low-Level Output Voltage (5 V) VOL 0.4 V Iout = -5 mA 7
Low-Level Output Voltage (3 V) VOL 0.4 V Iout = -5 mA 7
Input Leakage Current (5 V) Iin -10 1 10 µA typ printed ±1 7
3-State Leakage Current (5 V) IOZ -10 10 µA 7
Input Leakage Current (3 V) Iin -10 1 10 µA typ printed ±1 7
3-State Leakage Current (3 V) IOZ -10 10 µA 7
Positive Digital Power Supply VD+ 3.135 3.3 5.25 V 7
Positive Analog Power Supply VA+ 4.75 5 5.25 V 7
Negative Analog Power Supply AGND -0.25 0 0.25 V 7
Specified Temperature Range TA -40 85 °C 7
Master Clock Frequency, Internal Gate Oscillator MCLK 2.5 4.096 5 MHz Specified with 4.096 MHz clock; crystal XIN 2.5-5.0 MHz 8
Master Clock Duty Cycle 40 60 % 8
CPUCLK Duty Cycle 40 60 % External MCLK duty cycle 45% to 55% 8
Rise Time, Any Digital Input Except SCLK trise 50 µs 10% and 90% points 8
Rise Time, SCLK trise 1 µs 10% and 90% points 8
Rise Time, Any Digital Output trise 100 ns 10% and 90% points, 50 pF load 8
Fall Time, Any Digital Input Except SCLK tfall 50 µs 10% and 90% points 8
Fall Time, SCLK tfall 1 µs 10% and 90% points 8
Serial Clock Frequency SCLK 2 MHz 8
Serial Clock Pulse Width High t1 200 ns 8
Serial Clock Pulse Width Low t2 200 ns 8
CS Falling to SCLK Rising t3 50 ns 8
Data Set-up Time Prior to SCLK Rising t4 50 ns 8
Data Hold Time After SCLK Rising t5 100 ns 8
SCLK Falling Prior to CS Disable t6 100 ns 8
CS Falling to SDI Driving t7 20 50 ns 8
SCLK Falling to New Data Bit (hold time) t8 20 50 ns 8

CAD (KiCad official)

  • Symbol: CS5550-ISZ
  • Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
  • 3D model: SSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cs5550-isz-etched.step / cs5550-isz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs5550-isz.step / cs5550-isz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (24 pp, sha256 619df7b98e405d96, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF