component
CS5513-BSZR
Public Made by Adomby adom
Cirrus Logic Analog To Digital Converters (ADCs), SOIC-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
CS5513-BSZR
Cirrus Logic · Analog To Digital Converters (ADCs) · SOIC-8-208mil
CS5513-BSZR from Cirrus Logic, in a SOIC-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Voltage reference input, referenced to V-, that sets the reference for the on-chip modulator, with a VREF input range of 250 mV to 5 V. |
| 2 | AIN+ | input | Positive side of the differential analog input into the device. |
| 3 | AIN- | input | Negative side of the differential analog input into the device. |
| 4 | CS | input | Chip select: when low, SDO is active, and when high, SDO is placed in high-impedance and the device can enter sleep mode. |
| 5 | SCLK | input | Serial bit clock with Schmitt-trigger input; holding it high enters sleep mode, and on the CS5510/12 it also serves as the master clock. |
| 6 | V+ | power_in | Positive supply voltage. |
| 7 | V- | power_in | Negative supply voltage. |
| 8 | SDO | tri_state | Serial data output that goes to high impedance when CS = 1, with its logic-low level matching the active-low voltage on CS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cirrus Logic |
| Package | SOIC-8-208mil |
| Category | Data Converters |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Linearity Error (CS5512/13) | -0.0015 | 0.0007 | 0.0015 | % FS | 4 | ||
| No Missing Codes (CS5512/13) | 20 | Bits | 4 | ||||
| Bipolar Offset (CS5512/13) | -100 | 40 | 100 | LSB20 | Note 2 | 4 | |
| Input Range (Bipolar) /(AIN+ - AIN-)/(VREF - V-)/ | 72 | 80 | 88 | % VREF | 4 | ||
| Voltage Reference Input Range {(VREF) - (V-)} | 0.25 | 2.5 | V | Note 8: VREF referenced to V-, must be ≤ V+ | 5 | ||
| Supply Voltages {(V+) - (V-)} | 4.75 | 5 | 5.25 | V | 5 | ||
| DC Power Supply Current IV+ (CS5513) | IV+ | 385 | 500 | µA | Note 9: IV+ and IV- may differ due to CS pin current | 5 | |
| DC Power Supply Current IV- (CS5513) | IV- | 385 | 500 | µA | Note 9: IV+ and IV- may differ due to CS pin current | 5 | |
| Power Consumption (CS5513) | 1.9 | 2.7 | mW | Note 10: all outputs unloaded; all inputs CMOS levels | 5 | ||
| Input Current: CS | ICS | 1 | mA | Note 14 | 5 | ||
| Input Leakage Current SCLK | Iin | -10 | 0.015 | 10 | µA | 5 | |
| 3-State Leakage Current SCLK | IOZ | -10 | 10 | µA | 5 | ||
| DC Power Supply Positive (V+) | V+ | -0.3 | 6 | V | Note 16: 0.0 V ≤ (V+) - (V-) ≤ +6.0 V | 6 | |
| DC Power Supply Negative (V-) | V- | -6 | 0.3 | V | Note 16: 0.0 V ≤ (V+) - (V-) ≤ +6.0 V | 6 | |
| Input Current, Any Pin Except Supplies | IIN | -10 | 10 | mA | Notes 17, 18 | 6 | |
| Output Current | IOUT | -25 | 25 | mA | 6 | ||
| Package Power Dissipation | PDN | 400 | mW | Note 19 | 6 | ||
| Ambient Operating Temperature | TA | -40 | 85 | °C | 6 | ||
| Storage Temperature | Tstg | -65 | 150 | °C | 6 | ||
| Internal Oscillator Frequency | fosc | 32 | 64 | 100 | kHz | Note 23 | 8 |
| Serial Clock Frequency (CS5511/13) | SCLK | 2 | MHz | Note 24 | 8 | ||
| SCLK High to Enter Sleep | tSLP | 200 | 2000 | µs | Notes 24, 25 | 8 | |
| SCLK Low to Exit Sleep | tWAKE | 10 | µs | Notes 24, 25 | 8 | ||
| Rise Time CSB | trise | 50 | µs | Note 26 | 8 | ||
| Rise Time SCLK | trise | 1 | µs | Note 26 | 8 | ||
| Rise Time SDO | trise | 10 | ns | Note 26 | 8 | ||
| Fall Time CSB | tfall | 50 | µs | Note 26 | 8 | ||
| Fall Time SCLK | tfall | 1 | µs | Note 26 | 8 | ||
| Fall Time SDO | tfall | 10 | ns | Note 26 | 8 | ||
| Serial Clock Pulse Width High | t6 | 200 | ns | 8 | |||
| Serial Clock Pulse Width Low | t7 | 200 | ns | 8 | |||
| CS to Data Valid | t8 | 150 | ns | 8 | |||
| SCLK Falling to New Data Bit | t9 | 150 | ns | 8 | |||
| CS Rising to SDO Hi-Z | t10 | 150 | ns | 8 | |||
| CS Falling to SCLK Rising | t11 | 200 | ns | 8 |
CAD (KiCad official)
- Symbol:
CS5513-BSZR - Footprint:
Package_SO:SOIC-8_5.3x5.3mm_P1.27mm - 3D model: SOIC-8-208mil (KiCad packages3D, STEP)
- 3D model files:
cs5513-bszr-etched.step/cs5513-bszr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cs5513-bszr.step/cs5513-bszr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cirrus Logic datasheet (26 pp, sha256
3456a675706334d0, retrieved 2026-11-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).