CS51414EDR8G

{
  "slug": "cs51414edr8g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "cs51414edr8g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cs51414edr8g.kicad_sym",
    "cs51414edr8g.kicad_mod",
    "cs51414edr8g.glb",
    "cs51414edr8g.step",
    "cs51414edr8g.lbr",
    "docs/hero.png",
    "docs/cs51414edr8g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cs51414edr8g-hero.glb",
    "cs51414edr8g-hero.overlay.json",
    "cs51414edr8g-etched.glb"
  ],
  "component": {
    "mpn": "CS51414EDR8G",
    "manufacturer": "onsemi",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588936531411550208",
    "parts": {
      "symbol": "cs51414edr8g.kicad_sym",
      "footprint": "cs51414edr8g.kicad_mod",
      "model_3d": "cs51414edr8g-hero.glb",
      "model_3d_plain": "cs51414edr8g-etched.glb",
      "model_3d_step": "cs51414edr8g-etched.step",
      "model_3d_step_plain": "cs51414edr8g.step",
      "lbr": "cs51414edr8g.lbr"
    },
    "distributor_links": {
      "lcsc": "C462717"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T09:31:00Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "BOOST",
        "type": "power_in",
        "description": "The BOOST pin provides additional drive voltage to the on-chip NPN power transistor, and the resulting lower switch-on voltage improves efficiency; the datasheet rates BOOST at 40 V maximum and −0.3 V minimum."
      },
      {
        "number": "2",
        "name": "VIN",
        "type": "power_in",
        "description": "This pin is the main power input to the IC, which accommodates input voltages from 4.5 V to 40 V."
      },
      {
        "number": "3",
        "name": "VSW",
        "type": "output",
        "description": "This pin is the emitter connection of the on-chip NPN power transistor and the switch output to the inductor; it requires a catch diode and may see −1.0 V for less than 50 ns during switch flyback."
      },
      {
        "number": "4",
        "name": "BIAS",
        "type": "power_in",
        "description": "The BIAS pin connects to the on-chip power rail so most internal circuitry can run from the regulated output or an external 3.3 V to 6.0 V supply to improve efficiency, and it is left floating if this feature is not used."
      },
      {
        "number": "5",
        "name": "SHDNB",
        "type": "input",
        "description": "This active-low TTL-compatible shutdown input has an internal pull-up current source, and the IC enters sleep mode drawing less than 85 µA when the pin is pulled below 1.0 V; it may be left floating if shutdown is not required."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "This pin is the power return connection for the IC."
      },
      {
        "number": "7",
        "name": "VFB",
        "type": "input",
        "description": "This pin is the inverting input of the error amplifier, and if VFB falls below 0.29 V the oscillator frequency is divided by four and current limit folds back to about 1 A."
      },
      {
        "number": "8",
        "name": "VC",
        "type": "passive",
        "description": "This pin is the error amplifier output and PWM comparator input, and driving it should be avoided because on-chip test circuitry becomes active whenever current exceeding 0.5 mA is forced into the IC."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The SOIC-8 pinout is taken from the 'PACKAGE PIN DESCRIPTION' table on page 2, which gives SOIC-8 pi; Pins 4 and 5 differ by device variant. CS51414 is the Bias version per the product selection guide (; Pin types for BOOST, BIAS, and VC are not stated in the datasheet and were assigned by function (sup"
        ],
        "pages_sent": 8,
        "cost_usd": 0.0537,
        "at": "2026-10-18T09:29:24"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588936531411550208",
        "pages": 20,
        "sha256": "78b0f5888488b6f3",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cs51414edr8g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cs51414edr8g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5e61a3c037039312ee948e1ab453430f7d2891f251dd2253638698af2cf31de8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}