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CS48505AS

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Chipanalog RS-485 / RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS48505AS

Chipanalog · RS-485 / RS-422 ICs · SOIC-8

CS48505AS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RO output Receiver data output: goes high when VID is above VTH+ and low when VID is below VTH-, and is held at fail-safe high on an open, shorted or idle bus.
2 REB input Receiver enable, active low with an internal pull-up; when high or open the receiver output is high impedance.
3 DE input Driver enable, active high with an internal pull-down; the driver is disabled when DE is low or open.
4 DI input Driver data input with an internal pull-up to VCC; when the driver is enabled and DI is floating, A is driven high and B low.
5 GND power_in Ground reference for all device voltages; absolute voltages are referenced to GND.
6 A bidirectional Non-inverting bus input/output; bus pin voltage is limited to -8 V to 13 V (absolute maximum) with -7 V to 12 V input range, and ESD is ±20 kV HBM.
7 B bidirectional Inverting bus input/output; bus pin voltage is limited to -8 V to 13 V (absolute maximum) with -7 V to 12 V input range, and ESD is ±20 kV HBM.
8 VCC power_in Supply pin, 3.0 V to 5.5 V recommended (absolute maximum 7 V); a 100 nF to 220 nF decoupling capacitor should be placed as close to this pin as possible.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute max) VCC -0.5 7 V All voltages referenced to GND, peak 5
Bus voltage A, B (absolute max) VIO -8 13 V Bus pins A, B 5
Bus voltage difference A to B (absolute max) VIO_DIF -8 13 V 5
Logic input voltage DI, DE, REB (absolute max) VIO -0.3 0.33 V Printed as VCC + 0.33 as maximum; value is the offset from VCC 5
Logic output voltage RO (absolute max) VIO -0.3 0.33 V Printed as VCC + 0.33 as maximum; value is the offset from VCC 5
Junction temperature (absolute max) TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM, bus A, B to GND VESD -20 20 kV Human body model per ANSI/ESDA/JEDEC JS-001 5
ESD HBM, other pins VESD -8 8 kV Human body model per ANSI/ESDA/JEDEC JS-001 5
ESD CDM, all pins VESD -2 2 kV Charged device model per JEDEC JESD22-C101 5
ESD IEC 61000-4-2 contact, bus A, B to GND VESD -6 6 kV Contact discharge per IEC 61000-4-2 5
ESD IEC 61000-4-4 EFT, bus A, B to GND VEFT -4 4 kV Per IEC 61000-4-4 5
Supply voltage (recommended) VCC 3 5 5.5 V Referenced to GND 5
Bus input voltage (recommended) VIN -7 12 V 5
High-level input threshold VIH 2 V Printed maximum is VCC 5
Low-level input threshold VIL 0 0.8 V 5
Differential load resistance RL 54 Ω Single printed value; column assignment inferred 5
Data rate CS48505Ax 1/tUI 0.5 Mbps Single printed value; column assignment inferred 5
Operating ambient temperature TA -40 125 °C 5
Junction temperature (recommended) TJ -40 150 °C 5
Junction-to-ambient thermal resistance SOIC8 RθJA 120 °C/W SOIC8 package 5
Differential output voltage /VOD/ 1.5 3.6 V RL = 60Ω, -7V ≤ Vtest ≤ 12V, see Fig 8-1 6
Differential output voltage /VOD/ 2.1 3.6 V RL = 60Ω, -7V ≤ Vtest ≤ 12V, 4.5V ≤ VCC ≤ 5.5V, see Fig 8-1 6
Differential output voltage /VOD/ 2 4.2 V RL = 100Ω, CL = 50pF, see Fig 8-2 6
Differential output voltage change Δ/VOD/ -50 50 mV RL = 54Ω or 100Ω, CL = 50pF, see Fig 8-2 6
Common-mode output voltage VOC 1 3 V RL = 54Ω or 100Ω, CL = 50pF, see Fig 8-2; printed typical is VCC/2 6
Steady-state common-mode output voltage change ΔVOC(SS) -50 50 mV 6
Common-mode output voltage change, peak-to-peak VOC(PP) 450 mV Single printed value; column assignment inferred 6
Driver short-circuit output current /IOS/ 100 150 mA DE = VCC, -7V ≤ VO ≤ 12V, or A and B shorted 6
Bus input current II 75 125 µA DE = 0V, VCC = 0V or 5.5V, VI = 12V 6
Bus input current II -100 -40 µA DE = 0V, VCC = 0V or 5.5V, VI = -7V 6
Bus input impedance RI 96 kΩ VA = -7V, VB = 12V or VA = 12V, VB = -7V; single printed value, column inferred 6
Positive-going input threshold voltage VTH+ -110 -50 mV 6
Negative-going input threshold voltage VTH- -200 -140 mV 6
Input hysteresis voltage VHYS 30 mV Single printed value; column inferred 6
Output high-level voltage VOH -0.5 -0.3 V IOH = -4mA; printed as VCC - 0.5 and VCC - 0.3, values are offsets from VCC 6
Output low-level voltage VOL 0.2 0.4 V IOL = 4mA 6
High-impedance output current IOZR -1 1 µA REB = VCC, VO = 0V or VCC 6
Receiver short-circuit output current IOSR 95 mA REB = DE = 0V, see Fig 8-3; single printed value, column inferred 6
Input current DI, DE, REB IIN -5 5 µA 0V ≤ VIN ≤ VCC 6
Quiescent current, driver and receiver enabled ICC 900 1400 µA REB = 0V, DE = VCC, no load 6
Quiescent current, driver enabled, receiver off ICC 550 900 µA REB = VCC, DE = VCC, no load 6
Quiescent current, driver off, receiver enabled ICC 500 800 µA REB = 0V, DE = 0V, no load 6
Standby current, driver and receiver off ICC 5 µA REB = VCC, DE = 0V, DI = VCC, no load; single printed value, column inferred 6
Driver differential rise/fall time CS48505Ax tr, tf 150 500 ns RL = 54Ω, CL = 50pF, see Fig 8-4 7
Driver propagation delay CS48505Ax tPHL, tPLH 100 250 ns 7
Driver pulse width distortion CS48505Ax tSK(P) 10 ns /tPHL - tPLH/ 7
Driver disable time CS48505Ax tPHZ, tPLZ 10 30 ns See Fig 8-5 and Fig 8-6 7
Driver enable time CS48505Ax tPZH, tPZL 300 800 ns REB = 0V, see Fig 8-5 and Fig 8-6 7
Driver enable time CS48505Ax tPZH, tPZL 6 12 µs REB = VCC, see Fig 8-5 and Fig 8-6 7
Receiver output rise/fall time CS48505Ax tr, tf 10 20 ns CL = 15pF, see Fig 8-7 7
Receiver propagation delay CS48505Ax tPHL, tPLH 50 100 ns 7
Receiver pulse width distortion CS48505Ax tSK(P) 7 ns /tPHL - tPLH/ 7
Receiver disable time CS48505Ax tPHZ, tPLZ 30 60 ns See Fig 8-8 7
Receiver enable time CS48505Ax tPZH(1), tPZL(1), tPZH(2), tPZL(2) 50 100 ns DE = VCC, see Fig 8-8 and Fig 8-9 7
Receiver enable time CS48505Ax tPZH(1), tPZL(1), tPZH(2), tPZL(2) 6 12 µs DE = 0V, see Fig 8-8 and Fig 8-9 7
Thermal shutdown temperature TSD 170 °C 6
Thermal shutdown hysteresis TSD 20 °C 6

CAD (KiCad official)

  • Symbol: CS48505AS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cs48505as-etched.step / cs48505as-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs48505as.step / cs48505as.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 4cc3e4a98400ee1a, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF