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CS4382A-CQZR

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Cirrus Logic ADCs/DACs - Special Purpose, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS4382A-CQZR

Cirrus Logic · ADCs/DACs - Special Purpose · LQFP-48(7x7)

CS4382A-CQZR from Cirrus Logic, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DSDA2 input Direct Stream Digital input for channel pair 2 (A), used when the device operates in DSD mode.
2 DSDB1 input Direct Stream Digital input for channel pair 1 (B), used when the device operates in DSD mode.
3 DSDA1 input Direct Stream Digital input for channel pair 1 (A), used when the device operates in DSD mode.
4 VD power_in Digital power supply input for the internal digital section, recommended 2.37 V to 2.63 V (2.5 V typical), absolute maximum 3.2 V.
5 GND power_in Ground reference, to be connected to analog ground.
6 MCLK input Master clock input that clocks the delta-sigma modulator and digital filters.
7 LRCK(DSD_EN) input Left/right clock input at the audio sample rate Fs in PCM mode; in stand-alone mode holding it at logic 1 enters DSD mode.
8 SDIN1 input Serial audio data input for channel pair 1, two's complement format.
9 SCLK input Serial clock input for the serial audio interface.
10 TST passive Test pin that must be tied to analog ground.
11 SDIN2 input Serial audio data input for channel pair 2, two's complement format.
12 TST passive Test pin that must be tied to analog ground.
13 SDIN3 input Serial audio data input for channel pair 3, two's complement format.
14 SDIN4 input Serial audio data input for channel pair 4, two's complement format.
15 M2(SCL/CCLK) input Control port clock input (SCL in I²C mode, CCLK in SPI mode, needs external pull-up in I²C mode); M2 mode select in stand-alone mode.
16 M1(SDA/CDIN) bidirectional Control port data I/O (SDA in I²C mode, requires external pull-up; CDIN input in SPI mode); M1 mode select in stand-alone mode.
17 M0(AD0/CS) input I²C address bit 0 or SPI chip select; M0 mode select in stand-alone mode.
18 VLC power_in Control port interface power, sets the logic level of the control port, recommended 1.71 V to 5.25 V.
19 RST input Reset input; the device enters low-power mode and internal registers reset to defaults when low.
20 FILT+ output Positive voltage reference output for the internal sampling circuits, requires capacitive decoupling to analog ground.
21 VQ output Quiescent voltage filter output that must be capacitively coupled to analog ground and presents an appreciable source impedance, so DC loading alters performance.
22 MUTEC2 output Mute control output for external mute circuits to suppress clicks and pops on channel pairs 2, 3 and 4.
23 AOUTB4- output Differential analog output for channel pair 4 B (negative leg); full-scale level is given in the Analog Characteristics table.
24 AOUTB4+ output Differential analog output for channel pair 4 B (positive leg); full-scale level is given in the Analog Characteristics table.
25 AOUTA4+ output Differential analog output for channel pair 4 A (positive leg); full-scale level is given in the Analog Characteristics table.
26 AOUTA4- output Differential analog output for channel pair 4 A (negative leg); full-scale level is given in the Analog Characteristics table.
27 AOUTB3- output Differential analog output for channel pair 3 B (negative leg); full-scale level is given in the Analog Characteristics table.
28 AOUTB3+ output Differential analog output for channel pair 3 B (positive leg); full-scale level is given in the Analog Characteristics table.
29 AOUTA3+ output Differential analog output for channel pair 3 A (positive leg); full-scale level is given in the Analog Characteristics table.
30 AOUTA3- output Differential analog output for channel pair 3 A (negative leg); full-scale level is given in the Analog Characteristics table.
31 GND power_in Ground reference, to be connected to analog ground.
32 VA power_in Analog power supply input, recommended 4.75 V to 5.25 V (5.0 V typical), absolute maximum 6.0 V.
33 AOUTB2- output Differential analog output for channel pair 2 B (negative leg); full-scale level is given in the Analog Characteristics table.
34 AOUTB2+ output Differential analog output for channel pair 2 B (positive leg); full-scale level is given in the Analog Characteristics table.
35 AOUTA2+ output Differential analog output for channel pair 2 A (positive leg); full-scale level is given in the Analog Characteristics table.
36 AOUTA2- output Differential analog output for channel pair 2 A (negative leg); full-scale level is given in the Analog Characteristics table.
37 AOUTB1- output Differential analog output for channel pair 1 B (negative leg); full-scale level is given in the Analog Characteristics table.
38 AOUTB1+ output Differential analog output for channel pair 1 B (positive leg); full-scale level is given in the Analog Characteristics table.
39 AOUTA1+ output Differential analog output for channel pair 1 A (positive leg); full-scale level is given in the Analog Characteristics table.
40 AOUTA1- output Differential analog output for channel pair 1 A (negative leg); full-scale level is given in the Analog Characteristics table.
41 MUTEC1 output Mute control output for an external mute circuit to suppress clicks and pops on channel pair 1.
42 M3(DSD_SCLK) input Mode select M3 in stand-alone mode; serial clock input for the Direct Stream Digital audio interface.
43 VLS power_in Serial audio interface power, sets the logic level of the serial port, recommended 1.71 V to 5.25 V.
44 DSDB4 input Direct Stream Digital input for channel pair 4 (B), used when the device operates in DSD mode.
45 DSDA4 input Direct Stream Digital input for channel pair 4 (A), used when the device operates in DSD mode.
46 DSDB3 input Direct Stream Digital input for channel pair 3 (B), used when the device operates in DSD mode.
47 DSDA3 input Direct Stream Digital input for channel pair 3 (A), used when the device operates in DSD mode.
48 DSDB2 input Direct Stream Digital input for channel pair 2 (B), used when the device operates in DSD mode.

Key specifications

Parameter Value
Manufacturer Cirrus Logic
Package LQFP-48(7x7)
Category Data Acquisition
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Power Supply Analog Power VA 4.75 5 5.25 V 8
Digital Internal Power VD 2.37 2.5 2.63 V 8
Serial Data Port Interface Power VLS 1.71 5 5.25 V 8
Control Port Interface Power VLC 1.71 5 5.25 V 8
Ambient Operating Temperature (power applied), Commercial Grade (-CQZ) TA -40 85 °C Power applied; commercial grade (-CQZ) 8
DC Power Supply Analog Power VA -0.3 6 V 8
DC Power Supply Digital Internal Power VD -0.3 3.2 V 8
DC Power Supply Serial Data Port Interface Power VLS -0.3 6 V 8
DC Power Supply Control Port Interface Power VLC -0.3 6 V 8
Input Current Any Pin Except Supplies Iin -10 10 mA Any pin except supplies 8
Digital Input Voltage Serial Data Port Interface VIND-S -0.3 V Max printed as VLS + 0.4 V 8
Digital Input Voltage Control Port Interface VIND-C -0.3 V Max printed as VLC + 0.4 V 8
Ambient Operating Temperature (power applied) Top -55 125 °C Power applied 8
Storage Temperature Tstg -65 150 °C 8
Dynamic Range 24-bit A-weighted 108 114 dB VA=VLS=VLC=5 V; VD=2.5 V; TA=25°C; FS 48/96/192 kHz and DSD 9
Dynamic Range 24-bit Unweighted 105 111 dB VA=VLS=VLC=5 V; VD=2.5 V; TA=25°C; FS 48/96/192 kHz and DSD 9
Total Harmonic Distortion + Noise 24-bit 0 dB THD+N -100 -94 dB VA=VLS=VLC=5 V; VD=2.5 V; TA=25°C; FS 48/96/192 kHz and DSD; 24-bit, 0 dB 9
Total Harmonic Distortion + Noise 24-bit -60 dB THD+N -51 -45 dB VA=VLS=VLC=5 V; VD=2.5 V; TA=25°C; FS 48/96/192 kHz and DSD; 24-bit, -60 dB 9
Full-scale Differential Output Voltage VFS 128 132 136 %•VA VA=VLS=VLC=5 V; VD=2.5 V; TA=25°C; tested under max ac-load resistance 9
Power Supply Current Normal Operation, VA = 5 V IA 84 91 mA Normal operation, VA = 5 V (Note 4) 11
Power Supply Current Normal Operation, VD = 2.5 V ID 20 25 mA Normal operation, VD = 2.5 V (Note 4) 11
Power Dissipation Normal Operation 470 520 mW VA = 5 V, VD = 2.5 V; normal operation 11
Input Leakage Current Iin -10 10 µA Any pin except supplies (Note 13) 14
High-level Input Voltage Serial I/O VIH 70 %VLS Serial I/O 14
High-level Input Voltage Control I/O VIH 70 %VLC Control I/O 14
Low-level Input Voltage Serial I/O VIL 30 %VLS Serial I/O 14
Low-level Input Voltage Control I/O VIL 30 %VLC Control I/O 14
Low-level Output Voltage Control I/O 3.3 V, 5 V VOL 20 %VLC IOL = -1.2 mA; Control I/O = 3.3 V, 5 V 14
Low-level Output Voltage Control I/O 1.8 V, 2.5 V VOL 25 %VLC IOL = -1.2 mA; Control I/O = 1.8 V, 2.5 V 14
RST pin Low Pulse Width 1 ms After power-up (Note 14) 15
MCLK Frequency 1.024 55.2 MHz 15
MCLK Duty Cycle 45 55 % Note 15 15
Input Sample Rate LRCK Single-speed Mode Fs 4 54 kHz Single-speed mode 15
Input Sample Rate LRCK Double-speed Mode Fs 50 108 kHz Double-speed mode 15
Input Sample Rate LRCK Quad-speed Mode Fs 100 216 kHz Quad-speed mode 15
LRCK Duty Cycle 45 55 % 15
SCLK Duty Cycle 45 55 % 15
SCLK High Time tsckh 8 ns 15
SCLK Low Time tsckl 8 ns 15
LRCK Edge to SCLK Rising Edge tlcks 5 ns 15
SDIN Setup Time before SCLK Rising Edge tds 3 ns 15
SDIN Hold Time after SCLK Rising Edge tdh 5 ns 15
MCLK Duty Cycle (DSD mode) 40 60 % DSD mode 16
DSD_SCLK Pulse Width Low tsclkl 160 ns 16
DSD_SCLK Pulse Width High tsclkh 160 ns 16
DSD_SCLK Frequency (64x Oversampled) 1.024 3.2 MHz 64x oversampled 16
DSD_SCLK Frequency (128x Oversampled) 2.048 6.4 MHz 128x oversampled 16
DSD_A / DSD_B Valid to DSD_SCLK Rising Setup Time tsdlrs 20 ns 16
DSD_SCLK Rising to DSD_A or DSD_B Hold Time tsdh 20 ns 16
SCL Clock Frequency (I2C) fscl 100 kHz I2C format 17
SDA Setup Time to SCL Rising (I2C) tsud 250 ns I2C format 17
Fall Time SCL and SDA (I2C) tfc 300 ns I2C format 17
Rise Time of SCL and SDA (I2C) trc 1 µs I2C format 17
Acknowledge Delay from SCL Falling (I2C) tack 300 1000 ns I2C format 17
CCLK Clock Frequency (SPI) fsclk 6 MHz SPI format 18
Rise Time of CCLK and CDIN (SPI) tr2 100 ns FSCK < 1 MHz (Note 19) 18
Fall Time of CCLK and CDIN (SPI) tf2 100 ns FSCK < 1 MHz (Note 19) 18
Package Thermal Resistance Multi-layer θJA 48 °C/Watt Multi-layer 11
Package Thermal Resistance Two-layer θJA 65 °C/Watt Two-layer 11
Package Thermal Resistance Junction-to-Case θJC 15 °C/Watt 11

CAD (KiCad official)

  • Symbol: CS4382A-CQZR
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cs4382a-cqzr-etched.step / cs4382a-cqzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs4382a-cqzr.step / cs4382a-cqzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cirrus Logic datasheet (50 pp, sha256 acf1aebedb22ef2d, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF