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CS3815EO

Public Made by Adom

by adom

CRMICRO Audio Amplifiers, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS3815EO

CRMICRO · Audio Amplifiers · HTSSOP-28

CS3815EO from CRMICRO, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 STBY input TTL-compatible standby logic input with levels up to AVCC; pulling it low mutes the outputs and puts the device in standby, and it must not be left floating.
2 /FAULT output Open-drain output that flags short-circuit or DC-detect faults, pulled toward AVCC; short-circuit lock can auto-recover if /FAULT is tied to STBY, otherwise the fault must be reset through PVCC.
3 IN1+ input Channel 1 positive audio input; the absolute input voltage range is -0.3 V to 5.3 V.
4 IN1- input Channel 1 negative audio input; the absolute input voltage range is -0.3 V to 5.3 V.
5 G0 input Gain-select low bit, TTL-compatible with levels up to AVCC; together with G1 it selects 20, 26, 32 or 36 dB gain.
6 G1 input Gain-select high bit, TTL-compatible with levels up to AVCC; together with G0 it selects 20, 26, 32 or 36 dB gain.
7 AVCC power_in Analog supply; recommended range 8 V to 26 V, absolute maximum 30 V.
8 AGND power_in Analog ground, connected to the heatsink (thermal pad) on the PCB.
9 GVDD power_out Internally generated high-side gate-drive supply (6.2 V typical, 5.0 V to 6.8 V), which also powers the PLIMIT divider.
10 PLIMIT input Power-limit level input set by a resistor divider between GVDD and GND; connecting it directly to GVDD disables power limiting.
11 IN2- input Channel 2 negative audio input; the absolute input voltage range is -0.3 V to 5.3 V.
12 IN2+ input Channel 2 positive audio input; the absolute input voltage range is -0.3 V to 5.3 V.
13 NC unconnected No internal connection.
14 PBTL input Parallel-BTL (mono) mode select; high enables parallel BTL operation with the input on channel 2 and the speaker across the channel 1 and 2 outputs, and it must be grounded for normal BTL mode.
15 PVCC2 power_in Channel 2 power-stage supply, recommended 8 V to 26 V, internally connected to the channel 1 supply pins.
16 PVCC2 power_in Channel 2 power-stage supply, recommended 8 V to 26 V, internally connected to the channel 1 supply pins.
17 BS2+ input Channel 2 positive output high-side bootstrap connection.
18 OUT2+ output Channel 2 positive PWM output to the speaker through the output EMI filter.
19 PGND power_in Power ground for the output stage; output filter ground returns connect here.
20 OUT2- output Channel 2 negative PWM output to the speaker through the output EMI filter.
21 BS2- input Channel 2 negative output high-side bootstrap connection.
22 BS1- input Channel 1 negative output high-side bootstrap connection.
23 OUT1- output Channel 1 negative PWM output to the speaker through the output EMI filter.
24 PGND power_in Power ground for the output stage; output filter ground returns connect here.
25 OUT1+ output Channel 1 positive PWM output to the speaker through the output EMI filter.
26 BS1+ input Channel 1 positive output high-side bootstrap connection.
27 PVCC1 power_in Channel 1 power-stage supply, recommended 8 V to 26 V, internally connected to the channel 2 supply pins.
28 PVCC1 power_in Channel 1 power-stage supply, recommended 8 V to 26 V, internally connected to the channel 2 supply pins.
29 PowerPAD passive Exposed thermal pad on the package underside, to be soldered to PCB copper (with vias to the bottom layer) for heat dissipation.

Key specifications

Parameter Value
Manufacturer CRMICRO
Package HTSSOP-28
Category Amplifiers/Comparators
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage PVCC, AVCC -0.3 30 V 除非另有规定，Tamb= 25℃ 4
Input voltage STBY VIN -0.3 V 除非另有规定，Tamb= 25℃ 4
Input voltage STBY, G0, G1, PBTL, /FAULT VIN -0.3 V 除非另有规定，Tamb= 25℃ 4
Input voltage PLIMIT VIN -0.3 V 除非另有规定，Tamb= 25℃ 4
Input voltage IN2-, IN2+, IN1-, IN1+ VIN -0.3 5.3 V 除非另有规定，Tamb= 25℃ 4
Ambient operating temperature Tamb -20 85 ℃ 除非另有规定，Tamb= 25℃ 4
Storage temperature Tstg -65 150 ℃ 除非另有规定，Tamb= 25℃ 4
Load resistance R 3.2 除非另有规定，Tamb= 25℃ 4
Supply voltage VCC 8 26 V PVCC，AVCC 4
High-level input voltage VIH 2 V STBY，G0，G1，PBTL 4
Low-level input voltage VII 0.8 V STBY，G0，G1，PBTL 4
Low-level output voltage VOL 0.8 V /FAULT，RPULL-UP=100k，Vcc=18V 4
High-level input current IIH 50 μA STBY，G0，G1，PBTL；V1=2V，Vcc=18V 4
Low-level input current IIL 5 μA STBY，G0，G1，PBTL；V1=0.8V，Vcc=18V 4
Operating temperature TA -20 85 ℃ 4
Output offset voltage /Vos/ 1.5 15 mV VCC=24V，RL=16Ω；VI=0V，Gain=36dB 5
Gate drive voltage GVDD 5 6.2 6.8 V VCC=24V，RL=16Ω；IGVDD=100μA 5
Quiescent current Icc 45 70 mA VCC=24V，RL=16Ω；STBY=2V，无负载 5
Standby current ISTBY 150 400 μA VCC=24V，RL=16Ω；STBY=0.8V，无负载 5
Gain (G1=0.8V, G0=0.8V) G 19 20 21 dB VCC=24V，RL=16Ω；G1=0.8V，G0=0.8V 5
Gain (G1=0.8V, G0=2V) G 25 26 27 dB VCC=24V，RL=16Ω；G1=0.8V，G0=2V 5
Gain (G1=2V, G0=0.8V) G 31 32 33 dB VCC=24V，RL=16Ω；G1=2V，G0=0.8V 5
Gain (G1=2V, G0=2V) G 35 36 37 dB VCC=24V，RL=16Ω；G1=2V，G0=2V 5
Quiescent current Icc 25 50 mA VCC=12V，RL=8Ω；STBY=2V，无负载 5
Oscillation frequency (24V test set) fOSC 250 300 350 kHz VCC=24V，RL=16Ω 6
Oscillation frequency (12V test set) fOSC 250 300 350 kHz VCC=12V，RL=8Ω 6
Drain-source on-resistance, high-side (upper) rDS(on) 250 mΩ VCC=24V，RL=16Ω；Io=500mA，TJ=25°C 5
Drain-source on-resistance, low-side (lower) rDS(on) 250 mΩ VCC=24V，RL=16Ω；Io=500mA，TJ=25°C 5
Drain-source on-resistance, total rDS(on) 500 mΩ VCC=24V，RL=16Ω；Io=500mA，TJ=25°C 5
Turn-on time ton 16 ms VCC=24V，RL=16Ω；STBY=2V 5
Turn-off time toff 3 μs VCC=24V，RL=16Ω；STBY=0.8V 5
Standby current ISTBY 100 μA VCC=12V，RL=8Ω；STBY=0.8V，无负载 5
Supply ripple rejection kSVR -70 dB VCC=24V，RL=16Ω；1kHz，200mVpp纹波，Gain=20dB，输入交流耦合到地 6
Continuous output power Po 15 W VCC=24V，RL=16Ω；THD=0.5%（最大不削波功率），f=1kHz 6
Total harmonic distortion THD 0.1 % VCC=24V，RL=16Ω；f=1kHz，Po=7.5W 6
Output noise voltage Vn 65 μV VCC=24V，RL=16Ω；20~22kHz，加滤波器，Gain=20dB 6
Crosstalk CT -100 dB VCC=24V，RL=16Ω；Vo=1Vrms，Gain=20dB，f=1kHz 6
Signal-to-noise ratio SNR 102 dB VCC=24V，RL=16Ω；Gain=20dB时最大输出，THD＜1%，f=1kHz 6
Thermal protection temperature 150 ℃ 6
Thermal protection hysteresis 20 ℃ 6
Continuous output power (VCC=16V) Po 15 W THD=10%，f=1kHz，VCC=16V 6
Continuous output power (VCC=13V) Po 10 W THD=10%，f=1kHz，VCC=13V 6
Total harmonic distortion THD 0.06 % RL=8Ω，f=1kHz，Po=5W 6

CAD (KiCad official)

  • Symbol: CS3815EO
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: cs3815eo-etched.step / cs3815eo-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs3815eo.step / cs3815eo.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CRMICRO datasheet (12 pp, sha256 8a12b4ce770d597d, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF