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CS32F103VBT7

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CHIPSEA Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscs32f103vbt7factory-2.0.0extractor-text
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Contents

README

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CS32F103VBT7

CHIPSEA · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

CS32F103VBT7 from CHIPSEA, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5V-tolerant (FT) I/O, default function PE2, alternate TRACECK.
2 PE3 bidirectional 5V-tolerant (FT) I/O, default function PE3, alternate TRACED0.
3 PE4 bidirectional 5V-tolerant (FT) I/O, default function PE4, alternate TRACED1.
4 PE5 bidirectional 5V-tolerant (FT) I/O, default function PE5, alternate TRACED2.
5 PE6 bidirectional 5V-tolerant (FT) I/O, default function PE6, alternate TRACED3.
6 VDD power_in Digital supply pin for I/O and internal regulator, 2.0 to 3.6 V.
7 PC13/TAMPER_RTC bidirectional I/O powered via a switch limited to 3 mA; as output only one of PC13-15 at a time, 2 MHz max, 30 pF max load, no LED drive; alternate TAMPER-RTC.
8 PC14/OSC32_IN bidirectional I/O with 3 mA supply-switch output limits (2 MHz, 30 pF); alternate OSC32_IN for the 32.768 kHz crystal.
9 PC15/OSC32_OUT bidirectional I/O with 3 mA supply-switch output limits (2 MHz, 30 pF); alternate OSC32_OUT for the 32.768 kHz crystal.
10 VSS power_in Digital ground pin.
11 VDD power_in Digital supply pin, 2.0 to 3.6 V.
12 OSC_IN input Input of the 4-16 MHz HXT oscillator; default OSC_IN, also listed with PD0 as special function.
13 OSC_OUT output Output of the 4-16 MHz HXT oscillator; default OSC_OUT, also listed with PD1 as special function.
14 NRST bidirectional Active-low reset with permanent pull-up of about 80 kOhm; VIL max 0.8 V, VIH min 2 V.
15 PC0 bidirectional I/O, default PC0, alternate ADC12_IN10.
16 PC1 bidirectional I/O, default PC1, alternate ADC12_IN11.
17 PC2 bidirectional I/O, default PC2, alternate ADC12_IN12.
18 PC3 bidirectional I/O, default PC3, alternate ADC12_IN13.
19 VSSA power_in Analog ground for ADC, reset block, RC oscillators and PLL; must be connected to VSS.
20 VREF- power_in ADC negative reference voltage input (0 V, VSSA).
21 VREF+ power_in ADC positive reference voltage input, 2.4 V to VDDA.
22 VDDA power_in Analog supply 2.0 to 3.6 V (min 2.4 V when ADC is used); must be connected to VDD.
23 PA0-WKUP bidirectional I/O, default PA0; alternate WKUP, USART2_CTS, ADC12_IN0, TIM2_CH1_ETR; rising edge wakes from power-down.
24 PA1 bidirectional I/O, default PA1; alternate USART2_RTS, ADC12_IN1, TIM2_CH2.
25 PA2 bidirectional I/O, default PA2; alternate USART2_TX, ADC12_IN2, TIM2_CH3.
26 PA3 bidirectional I/O, default PA3; alternate USART2_RX, ADC12_IN3, TIM2_CH4.
27 VSS power_in Digital ground pin.
28 VDD power_in Digital supply pin, 2.0 to 3.6 V.
29 PA4 bidirectional I/O, default PA4; alternate SPI1_NSS, USART2_CK, ADC12_IN4.
30 PA5 bidirectional I/O, default PA5; alternate SPI1_SCK, ADC12_IN5.
31 PA6 bidirectional I/O, default PA6; alternate SPI1_MISO, ADC12_IN6, TIM3_CH1, TIM1_BKIN.
32 PA7 bidirectional I/O, default PA7; alternate SPI1_MOSI, ADC12_IN7, TIM3_CH2, TIM1_CHIN.
33 PC4 bidirectional I/O, default PC4, alternate ADC12_IN14.
34 PC5 bidirectional I/O, default PC5, alternate ADC12_IN15.
35 PB0 bidirectional I/O, default PB0; alternate ADC12_IN8, TIM3_CH3, TIM1_CH2N.
36 PB1 bidirectional I/O, default PB1; alternate ADC12_IN9, TIM3_CH4, TIM1_CH3N.
37 PB2/BOOT1 bidirectional 5V-tolerant (FT) I/O, default PB2 / BOOT1 boot-mode select.
38 PE7 bidirectional 5V-tolerant (FT) I/O, default PE7, alternate TIM1_ETR.
39 PE8 bidirectional 5V-tolerant (FT) I/O, default PE8, alternate TIM1_CH1N.
40 PE9 bidirectional 5V-tolerant (FT) I/O, default PE9, alternate TIM1_CH1.
41 PE10 bidirectional 5V-tolerant (FT) I/O, default PE10, alternate TIM1_CH2N.
42 PE11 bidirectional 5V-tolerant (FT) I/O, default PE11, alternate TIM1_CH2.
43 PE12 bidirectional 5V-tolerant (FT) I/O, default PE12, alternate TIM1_CH3N.
44 PE13 bidirectional 5V-tolerant (FT) I/O, default PE13, alternate TIM1_CH3.
45 PE14 bidirectional 5V-tolerant (FT) I/O, default PE14, alternate TIM1_CH4.
46 PE15 bidirectional 5V-tolerant (FT) I/O, default PE15, alternate TIM1_BKIN.
47 PB10 bidirectional 5V-tolerant (FT) I/O, default PB10; alternate I2C2_SCL, USART3_TX, TIM2_CH3.
48 PB11 bidirectional 5V-tolerant (FT) I/O, default PB11; alternate I2C2_SDA, USART3_RX, TIM2_CH4.
49 VSS power_in Digital ground pin.
50 VDD power_in Digital supply pin, 2.0 to 3.6 V.
51 PB12 bidirectional 5V-tolerant (FT) I/O, default PB12; alternate SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN.
52 PB13 bidirectional 5V-tolerant (FT) I/O, default PB13; alternate SPI2_SCK, USART3_CTS, TIM1_CH1N.
53 PB14 bidirectional 5V-tolerant (FT) I/O, default PB14; alternate SPI2_MISO, USART3_RTS, TIM1_CH2N.
54 PB15 bidirectional 5V-tolerant (FT) I/O, default PB15; alternate SPI2_MOSI, TIM1_CH3N.
55 PD8 bidirectional 5V-tolerant (FT) I/O, default PD8, remap USART3_TX.
56 PD9 bidirectional 5V-tolerant (FT) I/O, default PD9, remap USART3_RX.
57 PD10 bidirectional 5V-tolerant (FT) I/O, default PD10, remap USART3_CK.
58 PD11 bidirectional 5V-tolerant (FT) I/O, default PD11, remap USART3_CTS.
59 PD12 bidirectional 5V-tolerant (FT) I/O, default PD12, remap TIM4_CH1/USART3_RTS.
60 PD13 bidirectional 5V-tolerant (FT) I/O, default PD13, remap TIM4_CH2.
61 PD14 bidirectional 5V-tolerant (FT) I/O, default PD14, remap TIM4_CH3.
62 PD15 bidirectional 5V-tolerant (FT) I/O, default PD15, remap TIM4_CH4.
63 PC6 bidirectional 5V-tolerant (FT) I/O, default PC6, remap TIM3_CH1.
64 PC7 bidirectional 5V-tolerant (FT) I/O, default PC7, remap TIM3_CH2.
65 PC8 bidirectional 5V-tolerant (FT) I/O, default PC8, remap TIM3_CH3.
66 PC9 bidirectional 5V-tolerant (FT) I/O, default PC9, remap TIM3_CH4.
67 PA8 bidirectional 5V-tolerant (FT) I/O, default PA8; alternate USART1_CK, TIM1_CH1, MCO.
68 PA9 bidirectional 5V-tolerant (FT) I/O, default PA9; alternate USART1_TX, TIM1_CH2.
69 PA10 bidirectional 5V-tolerant (FT) I/O, default PA10; alternate USART1_RX, TIM1_CH3.
70 PA11 bidirectional 5V-tolerant (FT) I/O, default PA11; alternate USART1_CTS, USBDM, CANRX, TIM1_CH4.
71 PA12 bidirectional 5V-tolerant (FT) I/O, default PA12; alternate USART1_RTS, USBDP, CANTX, TIM1_ETR.
72 PA13 bidirectional 5V-tolerant (FT) I/O, reset function JTMS/SWDIO.
73 NC unconnected No connection.
74 VSS power_in Digital ground pin.
75 VDD power_in Digital supply pin, 2.0 to 3.6 V.
76 PA14 bidirectional 5V-tolerant (FT) I/O, reset function JTCK/SWCLK.
77 PA15 bidirectional 5V-tolerant (FT) I/O, reset function JTDI; remap TIM2_CH1_ETR, SPI1_NSS; SWJ must be disabled to use as GPIO.
78 PC10 bidirectional 5V-tolerant (FT) I/O, default PC10, remap USART3_TX.
79 PC11 bidirectional 5V-tolerant (FT) I/O, default PC11, remap USART3_RX.
80 PC12 bidirectional 5V-tolerant (FT) I/O, default PC12, remap USART3_CK.
81 PD0 bidirectional 5V-tolerant (FT) I/O PD0, remap CANRX; on LQFP100 PD0/PD1 are fixed-function so no remap needed (50 MHz output only).
82 PD1 bidirectional 5V-tolerant (FT) I/O PD1, remap CANTX; on LQFP100 PD0/PD1 are fixed-function (50 MHz output only).
83 PD2 bidirectional 5V-tolerant (FT) I/O, default PD2, alternate TIM3_ETR.
84 PD3 bidirectional 5V-tolerant (FT) I/O, default PD3, remap USART2_CTS.
85 PD4 bidirectional 5V-tolerant (FT) I/O, default PD4, remap USART2_RTS.
86 PD5 bidirectional 5V-tolerant (FT) I/O, default PD5, remap USART2_TX.
87 PD6 bidirectional 5V-tolerant (FT) I/O, default PD6, remap USART2_RX.
88 PD7 bidirectional 5V-tolerant (FT) I/O, default PD7, remap USART2_CK.
89 PB3 bidirectional 5V-tolerant (FT) I/O, reset function JTDO; alternate TRACESWO, TIM2_CH2, SPI1_SCK.
90 PB4 bidirectional 5V-tolerant (FT) I/O, reset function NJTRST; alternate TIM3_CH1, SPI1_MISO.
91 PB5 bidirectional I/O, default PB5; alternate I2C1_SMBA, TIM3_CH2, SPI1_MOSI.
92 PB6 bidirectional 5V-tolerant (FT) I/O, default PB6; alternate I2C1_SCL, TIM4_CH1, USART1_TX.
93 PB7 bidirectional 5V-tolerant (FT) I/O, default PB7; alternate I2C1_SDA, TIM4_CH2, USART1_RX.
94 BOOT0 input Boot mode select input, accepts 0 to 5.5 V.
95 PB8 bidirectional 5V-tolerant (FT) I/O, default PB8; alternate TIM4_CH3, remap I2C1_SCL/CANRX.
96 PB9 bidirectional 5V-tolerant (FT) I/O, default PB9; alternate TIM4_CH4, remap I2C1_SDA/CANTX.
97 PE0 bidirectional 5V-tolerant (FT) I/O, default PE0, alternate TIM4_ETR.
98 PE1 bidirectional 5V-tolerant (FT) I/O, default PE1, no alternate function listed.
99 VSS power_in Digital ground pin.
100 VDD power_in Digital supply pin, 2.0 to 3.6 V.

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (including VDDA and VDD) VDD, VSS -0.3 4 V 24
Input voltage on 5V-tolerant pins VIN -0.3 5.5 V VSS -0.3 to 5.5 24
Input voltage on other pins VIN -0.3 4 V VSS -0.3 to 4.0 24
Voltage difference between different supply pins /ΔVDDx/ 50 mV 24
Voltage difference between different ground pins /VSSX, VSS/ 50 mV 24
USB transceiver startup time tSTARTUP 1 μs 44
USB operating voltage VDD 3 3.6 V 44
USB differential input sensitivity VDI 0.2 V I(USBDP,USBDM) 44
USB differential common mode range VCM 0.8 2.5 V Includes VDI range 44
USB single-ended receiver threshold VSE 1.3 2 V 44
USB static output low level VOL 0.3 V RL of 1.5kΩ to 3.6V 44
USB static output high level VOH 2.8 3.6 V RL of 15kΩ to VSS 44
USB rise time tr 4 20 ns CL ≤ 50pF 45
USB fall time tf 4 20 ns CL ≤ 50pF 45
Rise/fall time matching trfm 90 110 % tr / tf 45
Output signal crossover voltage VCRS 1.3 2 V 45
ADC supply voltage VDDA 2.4 3.6 V 45
ADC positive reference voltage VREF+ 2.4 V max is VDDA 45
Current on VREF input pin IVREF 160 220 μA 45
ADC clock frequency fADC 0.6 14 MHz 45
Sampling rate fS 0.05 1 MHz 45
External trigger frequency fTRIG 823 kHz fADC=14MHz 45
Conversion voltage range VAIN 0 V max is VREF+; 0 (VSSA or VREF- connected to ground) 45
External input impedance RAIN 50 kΩ 45
Sampling switch resistance RADC 1 kΩ 45
Internal sample and hold capacitor CADC 8 pF 45
Injected trigger conversion latency tlat 0.214 μs fADC=14MHz 46
Regular trigger conversion latency tlatr 0.143 μs fADC=14MHz 46
Sampling time ts 0.107 17.1 μs fADC=14MHz 46
Power-up time tSTAB 0 0 1 μs 46
Total conversion time (including sampling time) tCONV 1 18 μs fADC=14MHz 46
Total error ET 1.3 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
Offset error EO 1 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
Gain error EG 0.5 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
Differential linearity error ED 0.7 1 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46
Integral linearity error EL 1.5 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN< 10 kΩ, VDDA = 3.3V, TA= 25 °C, after ADC calibration 46

CAD (KiCad official)

  • Symbol: CS32F103VBT7
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cs32f103vbt7-etched.step / cs32f103vbt7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32f103vbt7.step / cs32f103vbt7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (66 pp, sha256 6da1e5b0c25b8892, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF