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CS32F103CBW6

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CHIPSEA Microcontrollers (MCU/MPU/SOC), QFN-48(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscs32f103cbw6factory-2.0.0extractor-text

Verified CS32F103CBW6

by Ray · last 8 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

8 Nov 2026RayPublished by the parts factory: tier lcsc, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CS32F103CBW6 · QFN-48(5x5) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 66-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-v1t5_s7a/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cs32f103cbw6.kicad_sym✓ cs32f103cbw6.kicad_mod✓ cs32f103cbw6.step
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CS32F103CBW6

CHIPSEA · Microcontrollers (MCU/MPU/SOC) · QFN-48(5x5)

CS32F103CBW6 from CHIPSEA, in a QFN-48(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital supply pin for I/O and the internal regulator, 2.0-3.6 V.
2 PC13/TAMPER-RTC bidirectional GPIO PC13 with TAMPER-RTC function, powered through a switch that sinks only 3 mA, so as an output it is limited to 2 MHz, 30 pF and cannot source current.
3 PC14/OSC32_IN bidirectional GPIO PC14 or 32.768 kHz oscillator input OSC32_IN, with the same 3 mA switch-powered output limits as PC13.
4 PC15/OSC32_OUT bidirectional GPIO PC15 or 32.768 kHz oscillator output OSC32_OUT, with the same 3 mA switch-powered output limits as PC13.
5 OSC_IN input 4-16 MHz crystal oscillator input after reset; software can reconfigure it as PD0.
6 OSC_OUT output 4-16 MHz crystal oscillator output after reset; software can reconfigure it as PD1.
7 NRST bidirectional Active-low device reset with internal weak pull-up (about 80 kΩ); input low level max 0.8 V.
8 VSSA power_in Analog ground for ADC, reset block, RC oscillators and PLL; must be connected to VSS.
9 VDDA power_in Analog supply 2.0-3.6 V (not below 2.4 V when ADC is used); must be connected to VDD.
10 PA0-WKUP bidirectional GPIO PA0 with WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR alternate functions.
11 PA1 bidirectional GPIO PA1 with USART2_RTS, ADC12_IN1 and TIM2_CH2 alternate functions.
12 PA2 bidirectional GPIO PA2 with USART2_TX, ADC12_IN2 and TIM2_CH3 alternate functions.
13 PA3 bidirectional GPIO PA3 with USART2_RX, ADC12_IN3 and TIM2_CH4 alternate functions.
14 PA4 bidirectional GPIO PA4 with SPI1_NSS, USART2_CK and ADC12_IN4 alternate functions.
15 PA5 bidirectional GPIO PA5 with SPI1_SCK and ADC12_IN5 alternate functions.
16 PA6 bidirectional GPIO PA6 with SPI1_MISO, ADC12_IN6, TIM3_CH1 and remap TIM1_BKIN.
17 PA7 bidirectional GPIO PA7 with SPI1_MOSI, ADC12_IN7, TIM3_CH2 and remap TIM1_CHIN.
18 PB0 bidirectional GPIO PB0 with ADC12_IN8, TIM3_CH3 and remap TIM1_CH2N.
19 PB1 bidirectional GPIO PB1 with ADC12_IN9, TIM3_CH4 and remap TIM1_CH3N.
20 PB2/BOOT1 bidirectional 5 V-tolerant GPIO PB2, also serves as BOOT1 boot mode select.
21 PB10 bidirectional 5 V-tolerant GPIO PB10 with I2C2_SCL, USART3_TX and remap TIM2_CH3.
22 PB11 bidirectional 5 V-tolerant GPIO PB11 with I2C2_SDA, USART3_RX and remap TIM2_CH4.
23 VSS power_in Digital ground.
24 VDD power_in Digital supply pin, 2.0-3.6 V.
25 PB12 bidirectional 5 V-tolerant GPIO PB12 with SPI2_NSS, I2C2_SMBA, USART3_CK and TIM1_BKIN.
26 PB13 bidirectional 5 V-tolerant GPIO PB13 with SPI2_SCK, USART3_CTS and TIM1_CH1N.
27 PB14 bidirectional 5 V-tolerant GPIO PB14 with SPI2_MISO, USART3_RTS and TIM1_CH2N.
28 PB15 bidirectional 5 V-tolerant GPIO PB15 with SPI2_MOSI and TIM1_CH3N.
29 PA8 bidirectional 5 V-tolerant GPIO PA8 with USART1_CK, TIM1_CH1 and MCO.
30 PA9 bidirectional 5 V-tolerant GPIO PA9 with USART1_TX and TIM1_CH2.
31 PA10 bidirectional 5 V-tolerant GPIO PA10 with USART1_RX and TIM1_CH3.
32 PA11 bidirectional 5 V-tolerant GPIO PA11 with USART1_CTS, USBDM, CANRX and TIM1_CH4.
33 PA12 bidirectional 5 V-tolerant GPIO PA12 with USART1_RTS, USBDP, CANTX and TIM1_ETR.
34 PA13 bidirectional 5 V-tolerant GPIO; reset function is JTMS/SWDIO.
35 VSS power_in Digital ground.
36 VDD power_in Digital supply pin, 2.0-3.6 V.
37 PA14 bidirectional 5 V-tolerant GPIO; reset function is JTCK/SWCLK.
38 PA15 bidirectional 5 V-tolerant GPIO; JTDI by default (SWJ must be disabled to use as GPIO), with TIM2_CH1_ETR and SPI1_NSS remap.
39 PB3 bidirectional 5 V-tolerant GPIO; JTDO by default, with TRACESWO, TIM2_CH2 and SPI1_SCK remap.
40 PB4 bidirectional 5 V-tolerant GPIO; NJTRST by default, with TIM3_CH1 and SPI1_MISO remap.
41 PB5 bidirectional GPIO PB5 with I2C1_SMBA and remap TIM3_CH2/SPI1_MOSI.
42 PB6 bidirectional 5 V-tolerant GPIO PB6 with I2C1_SCL, TIM4_CH1 and remap USART1_TX.
43 PB7 bidirectional 5 V-tolerant GPIO PB7 with I2C1_SDA, TIM4_CH2 and remap USART1_RX.
44 BOOT0 input Boot mode select input, input voltage range 0-5.5 V.
45 PB8 bidirectional 5 V-tolerant GPIO PB8 with TIM4_CH3 and remap I2C1_SCL/CANRX.
46 PB9 bidirectional 5 V-tolerant GPIO PB9 with TIM4_CH4 and remap I2C1_SDA/CANTX (printed as 'P89' in the table).
47 VSS power_in Digital ground.
48 VDD power_in Digital supply pin, 2.0-3.6 V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package QFN-48(5x5)
Category Embedded Processors & Controllers
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage (VDD, VDDA) VDD, VSS -0.3 4 V 24
Input voltage on 5V-tolerant pins VIN 5.5 V 5V-tolerant pins 24
Input voltage on other pins VIN 4 V 24
Voltage difference between supply pins /ΔVDDx/ 50 mV 24
Voltage difference between ground pins /VSSX, VSS/ 50 mV 24
ADC supply voltage VDDA 2.4 3.6 V 45
Positive reference voltage VREF+ 2.4 V 45
Current into VREF input pin IVREF 160 220 μA 45
ADC clock frequency fADC 0.6 14 MHz 45
Sampling rate fS 0.05 1 MHz 45
External trigger frequency fTRIG 823 kHz fADC=14MHz 45
External trigger frequency fTRIG 17 1/fADC 45
Conversion voltage range VAIN 0 V VSSA or VREF- connected to ground 45
External input impedance RAIN 50 kΩ 45
Sampling switch resistance RADC 1 kΩ 45
Internal sample and hold capacitance CADC 8 pF 45
Injected trigger conversion latency tlat 0.214 μs fADC=14MHz 46
Injected trigger conversion latency tlat 3 1/fADC 46
Regular trigger conversion latency tlatr 0.143 μs fADC=14MHz 46
Regular trigger conversion latency tlatr 2 1/fADC 46
Sampling time ts 0.107 17.1 μs fADC=14MHz 46
Sampling time ts 1.5 239.5 1/fADC 46
ADC power-up time tSTAB 0 0 1 μs 46
Total conversion time including sampling tCONV 1 18 μs fADC=14MHz 46
Total conversion time including sampling tCONV 14 252 1/fADC 46
Comprehensive error ET -2 1.3 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration 46
Offset error EO -1.5 1 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration 46
Gain error EG -1.5 0.5 1.5 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration 46
Differential linearity error ED -1 0.7 1 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration 46
Integral linearity error EL -2 1.5 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V, TA = 25 °C, measured after ADC calibration 46
USB operating voltage VDD 3 3.6 V 44
Differential input sensitivity VDI 0.2 V I(USBDP,USBDM) 44
Differential common-mode range VCM 0.8 2.5 V 包含VDI范围 44
Single-ended receiver threshold VSE 1.3 2 V 44
Static output low level VOL 0.3 V 1.5kΩ RL connected to 3.6V 44
Static output high level VOH 2.8 3.6 V 15kΩ RL connected to VSS 44
USB transceiver startup time tSTARTUP 1 μs 44
Data signal rise time tr 4 20 ns CL ≤ 50pF 45
Data signal fall time tf 4 20 ns CL ≤ 50pF 45
Rise/fall time matching trfm 90 110 % 45
Output signal crossover voltage VCRS 1.3 2 V 45

CAD (KiCad official)

  • Symbol: CS32F103CBW6
  • Footprint: Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm
  • 3D model: QFN-48(5x5) (KiCad packages3D, STEP)
  • 3D model files: cs32f103cbw6-etched.step / cs32f103cbw6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32f103cbw6.step / cs32f103cbw6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (66 pp, sha256 f311f0d25fd53b08, retrieved 2026-11-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF