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CS32F035F6P7

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CHIPSEA Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CS32F035F6P7

CHIPSEA · Microcontrollers (MCU/MPU/SOC) · TSSOP-20

CS32F035F6P7 from CHIPSEA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT0 input Boot memory selection pin.
2 PF0/HXT_IN bidirectional Port F0 pin that doubles as the HXT_IN external high-speed crystal oscillator input.
3 PF1/HXT_OUT bidirectional Port F1 pin that doubles as the HXT_OUT external high-speed crystal oscillator output.
4 NRST bidirectional Reset input and internal reset output, with weak pull-up resistor, active low.
5 VDDA power_in Analog power supply.
6 PA0 bidirectional Port A0 multiplexed with USART2_CTS, ADC_IN0 and WKUP1.
7 PA1 bidirectional Port A1 multiplexed with EVENTOUT, USART2_RTS and ADC_IN1.
8 PA2 bidirectional Port A2 multiplexed with USART2_TX and ADC_IN2.
9 PA3 bidirectional Port A3 multiplexed with USART2_RX and ADC_IN3.
10 PA4 bidirectional Port A4 multiplexed with SPI1_NSS, TIM14_CH1, USART2_CK and ADC_IN4.
11 PA5 bidirectional Port A5 multiplexed with SPI1_SCK and ADC_IN5.
12 PA6 bidirectional Port A6 multiplexed with SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT and ADC_IN6.
13 PA7 bidirectional Port A7 multiplexed with SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT and ADC_IN7.
14 PB1 bidirectional Port B1 multiplexed with TIM3_CH4, TIM14_CH1, TIM1_CH3N and ADC_IN9.
15 GND power_in Ground.
16 VDD power_in Digital power supply.
17 PA9 bidirectional Port A9 multiplexed with USART1_TX, TIM1_CH2, I2C1_SCL and CKO; supports Fast mode Plus.
18 PA10 bidirectional Port A10 multiplexed with USART1_RX, TIM1_CH3, TIM17_BKIN and I2C1_SDA; supports Fast mode Plus.
19 PA13 (SWDIO) bidirectional Port A13 multiplexed with IR_OUT and SWDIO; after reset it is configured as SWDIO with internal pull-up enabled.
20 PA14 (SWCLK) bidirectional Port A14 multiplexed with USART2_TX and SWCLK; after reset it is configured as SWCLK with internal pull-down enabled.

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package TSSOP-20
Category Embedded Processors & Controllers
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD voltage to GND VDD -0.3 6 V The voltage between VDD and GND 29
VDDA voltage to GND VDDA -0.3 6 V The voltage between VDDA and GND 29
VBAT voltage to GND VBAT -0.3 6 V The voltage between VBAT and GND 29
VDD-VDDA voltage difference VDD-VDDA 0.4 V The voltage between VDD and VDDA 29
Voltage on I/O pins Vi/o -0.3 6 V The voltage on the I/O pins; min printed as GND- 0.3 29
Storage temperature Tstorage -65 150 ℃ 29
Junction temperature Tjunction 150 ℃ 29
Total current into all VDD power lines Itotal-pwr 120 mA 29
Total current out of all GND power lines Itotal-GND -120 mA 29
Current into each power pin Ipwr-pin 100 mA 29
Current out of each GND pin IGND-pin -100 mA 29
Total current into all I/O pins Itotal-sunk 80 mA 29
Total current out of all I/O pins Itotal-source -80 mA 29
Current into any I/O pin Isunk-pin 25 mA 29
Current out of any I/O pin Isource-pin -25 mA 29
Operating voltage range of power supply VDD VVDD-range 2 5.5 V 29
Operating voltage range of power supply VDDA VVDDA-range 2 5.5 V 29
Operating ambient temperature range Trange -40 85 ℃ case1 29
Operating ambient temperature range Trange -40 105 ℃ case2 29
Junction temperature range Tjunction-range -40 105 ℃ case1 29
Junction temperature range Tjunction-range -40 125 ℃ case2 29
Internal AHB clock frequency range fAHB-clock 0 48 MHz 29
Internal APB clock frequency range fAPB-clock 0 48 MHz 29
I/O input voltage range VIO-range -0.3 5.5 V 29
VDD/VDDA supply fall rate Tsupply-fall 20 uS/V 29
Supply VDD power on reset threshold TVDD-POR 1.84 1.92 2 V 29
Supply VDD power down reset threshold TVDD-fall 1.8 1.88 1.96 V 29
Supply VDDA power down reset threshold TVDDA-fall 1.8 1.88 1.96 V 29
Reset temporization Treset-tempo 4.2 10 mS VVDD-range≤5.5V 29
Reset temporization Treset-tempo 4.2 7.5 mS VVDD-range≤3.6V 29
LVD stage-0 falling threshold voltage VLVD 2.01 2.08 2.15 V 29
LVD stage-0 rising threshold voltage VLVD 2.11 2.18 2.25 V 29
Internal reference voltage Vrefint 1.19 1.22 1.25 V 34
Internal reference voltage variation over temperature range deltVrefint 11 mV over the temperature range 34
Internal reference voltage temperature coefficient Tc -60 60 ppm/0C 34
Output low level voltage VOL 1.1 V /Isunk-pin/=20mA, VDD≥2.7V 30
Output low level voltage VOL 0.36 V /Isunk-pin/=6mA 30
I/O pull-up resistance Rpull-up 17 40 140 Ω 30
I/O pull-down resistance Rpull-down 15 40 154 Ω 30
Frequency of HXT crystal oscillator fHXT-IN 4 8 32 MHz 32
Crystal load capacitance of HXT CLHXT 5 10 20 pF 32
HXT external source clock frequency FHXT-IN 8 32 MHz 33
Frequency of PLL input clock fPLL-IN 1 8 24 MHz 33
Frequency of PLL output clock fPLL-OUT 16 48 MHz 33
Lock time of PLL Tlock 200 uS 33
HRC accuracy of frequency faccuracy-HRC -1 1 % 31
Power dissipation of HRC Ipd-HRC 44 66 102 uA 31
HRC temperature characteristics of frequency ftemp-HRC -2 2 % 31
Frequency of LRC fLRC 30 40 50 KHz 32
Wake-up time from deepsleep1 mode Twk-deepsleep1 3 5.3 uS 31
VDDA power supply range for ADC VDDA 2.4 5.5 V 35
ADC programmable resolution Resolution 6 12 Bit 35
ADC absolute error ERRabsolute -4 3.3 4 LSB 35
Average slope of temperature sensor voltage Stemp 4.35 4.47 4.6 mV/℃ 35
Temperature sensor voltage of 30±5℃ Vtemp30 1.37 1.43 1.5 V 30±5℃ 35
Sector endurance Cycendurance 20000 Cycles 36
Electrostatic discharge voltage, human body model VESD-HBM 4000 V MIL-STD-883E, Trange=23±5℃, RH 55%±10% 39
Latch-up current, JEDEC STANDARD NO.78C Ilatchup 200 mA Trange=105±5℃, RH 55%±10% 39
Thermal resistance junction-to-ambient, TSSOP20 (2S2P) ΘJA 103 ℃/W by 2S2P 44
Thermal resistance junction-to-case, TSSOP20 ΘJC 35.7 ℃/W 44

CAD (KiCad official)

  • Symbol: CS32F035F6P7
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: cs32f035f6p7-etched.step / cs32f035f6p7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32f035f6p7.step / cs32f035f6p7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (51 pp, sha256 73c7f13a1702150d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF