# CS32F031K8S6-RA

**CHIPSEA** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

CS32F031K8S6-RA from CHIPSEA, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Digital supply pin that powers the I/O, regulator and HXT module, with a voltage range of 2.0V to 5.5V. |
| 2 | PF0/HXT_IN | bidirectional | GPIO PF0 that doubles as the HXT crystal oscillator input for a 4 to 32MHz crystal. |
| 3 | PF1/HXT_OUT | bidirectional | GPIO PF1 that doubles as the HXT crystal oscillator output for a 4 to 32MHz crystal. |
| 4 | NRST | input | Active-low reset input (also internal reset output); after POR reset release NRST must be held at least 9ms or FWDT may be enabled. |
| 5 | VDDA | power_in | Analog supply for ADC, HRC, HRC14, PLL, POR/PDR and LVD, ranging from VDD up to 5.5V and above 2.4V when the ADC is active. |
| 6 | PA0 | bidirectional | GPIO PA0 that can serve as ADC input channel ADC_IN0 or USART2_CTS, and as WKUP1 wake-up input. |
| 7 | PA1 | bidirectional | GPIO PA1 that can serve as ADC input channel ADC_IN1 or EVENTOUT, and as USART2_RTS. |
| 8 | PA2 | bidirectional | GPIO PA2 that can serve as ADC input channel ADC_IN2, USART2_TX or TIM15_CH1. |
| 9 | PA3 | bidirectional | GPIO PA3 that can serve as ADC input channel ADC_IN3, USART2_RX or TIM15_CH2. |
| 10 | PA4 | bidirectional | GPIO PA4 that can serve as ADC input channel ADC_IN4, SPI1_NSS, USART2_CK or TIM14_CH1. |
| 11 | PA5 | bidirectional | GPIO PA5 that can serve as ADC input channel ADC_IN5 or SPI1_SCK. |
| 12 | PA6 | bidirectional | GPIO PA6 that can serve as ADC input channel ADC_IN6, SPI1_MISO, TIM3_CH1 or TIM1_BKIN. |
| 13 | PA7 | bidirectional | GPIO PA7 that can serve as ADC input channel ADC_IN7, SPI1_MOSI, TIM3_CH2 or TIM14_CH1. |
| 14 | PB0 | bidirectional | GPIO PB0 that can serve as ADC input channel ADC_IN8, TIM3_CH3, TIM1_CH2N or EVENTOUT. |
| 15 | PB1 | bidirectional | GPIO PB1 that can serve as ADC input channel ADC_IN9, TIM3_CH4, TIM14_CH1 or TIM1_CH3N. |
| 16 | GND | power_in | Chip ground pin for the digital supply domain. |
| 17 | VDD | power_in | Digital supply pin that powers the I/O, regulator and HXT module, with a voltage range of 2.0V to 5.5V. |
| 18 | PA8 | bidirectional | GPIO PA8 that can serve as USART1_CK, TIM1_CH1, EVENTOUT or CKO clock output. |
| 19 | PA9 | bidirectional | GPIO PA9 that can serve as USART1_TX, TIM1_CH2, I2C1_SCL or CKO, and supports I2C Fast-mode Plus. |
| 20 | PA10 | bidirectional | GPIO PA10 that can serve as USART1_RX, TIM1_CH3, TIM17_BKIN or I2C1_SDA, and supports I2C Fast-mode Plus. |
| 21 | PA11 | bidirectional | GPIO PA11 that can serve as USART1_CTS, TIM1_CH4 or EVENTOUT. |
| 22 | PA12 | bidirectional | GPIO PA12 that can serve as USART1_RTS, TIM1_ETR or EVENTOUT. |
| 23 | PA13 | bidirectional | GPIO PA13 that after reset is configured as SWDIO, with internal pull-up enabled on the SWDIO pin; it can also serve as IR_OUT. |
| 24 | PA14 | bidirectional | GPIO PA14 that after reset is configured as SWCLK, with internal pull-down enabled on the SWCLK pin; it can also serve as USART2_TX. |
| 25 | PA15 | bidirectional | GPIO PA15 with injection-current (anti back-feed) capability, that can serve as SPI1_NSS, USART2_RX or EVENTOUT. |
| 26 | PB3 | bidirectional | GPIO PB3 with injection-current (anti back-feed) capability, that can serve as SPI1_SCK or EVENTOUT. |
| 27 | PB4 | bidirectional | GPIO PB4 with injection-current (anti back-feed) capability, that can serve as SPI1_MISO, TIM3_CH1 or EVENTOUT. |
| 28 | PB5 | bidirectional | GPIO PB5 with injection-current (anti back-feed) capability, that can serve as SPI1_MOSI, I2C1_SMBA, TIM16_BKIN or TIM3_CH2. |
| 29 | PB6 | bidirectional | GPIO PB6 with injection-current (anti back-feed) capability, that can serve as I2C1_SCL, USART1_TX or TIM16_CH1N, and supports I2C Fast-mode Plus. |
| 30 | PB7 | bidirectional | GPIO PB7 with injection-current (anti back-feed) capability, that can serve as I2C1_SDA, USART1_RX or TIM17_CH1N, and supports I2C Fast-mode Plus. |
| 31 | BOOT0 | input | Boot mode selection pin; a low level at BOOT0 selects boot from Flash, and the low-level input voltage limit is 0.3*VDD-0.3V. |
| 32 | GND | power_in | Chip ground pin for the digital supply domain. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CHIPSEA |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD 和 GND 之间的电压 | VDD | -0.3 |  | 6 | V |  | 28 |
| VDDA 和 GND 之间的电压 | VDDA | -0.3 |  | 6 | V |  | 28 |
| VDD 和 VDDA 之间的电压 | VDD-VDDA |  |  | 0.4 | V |  | 28 |
| I/O 管脚电压 | Vi/o |  |  | 6 | V |  | 28 |
| 存储温度 | Tstorage | -65 |  | 150 | ℃ |  | 28 |
| 结温 | Tjunction |  |  | 150 | ℃ |  | 28 |
| 流入 VDD 电源线的总电流 | Itotal-pwr |  |  | 120 | mA |  | 28 |
| 流出 GND 接地线的总电流 | Itotal-GND | -120 |  |  | mA |  | 28 |
| 流入每个电源管脚的电流 | Ipwr-pin |  |  | 100 | mA |  | 28 |
| 流入每个地管脚的电流 | IGND-pin | -100 |  |  | mA |  | 28 |
| 流入所有 I/O 管脚的总电流 | Itotal-sunk |  |  | 80 | mA |  | 28 |
| 流出所有 I/O 管脚的总电流 | Itotal-source | -80 |  |  | mA |  | 28 |
| 流入任意一个 I/O 管脚的电流 | Isunk-pin |  |  | 25 | mA |  | 28 |
| 流出任意一个 I/O 管脚的总电流 | Isource-pin | -25 |  |  | mA |  | 28 |
| VDD 的工作电压范围 | VVDD-range | 2 |  | 5.5 | V |  | 28 |
| VDDA 的工作电压范围 | VVDDA-range | 2 |  | 5.5 | V |  | 28 |
| 芯片环境温度 | Trange | -40 |  | 85 | ℃ |  | 28 |
| 芯片结温范围 | Tjunction-range | -40 |  | 125 | ℃ |  | 28 |
| 内部 AHB 时钟频率 | fAHB-clock | 0 |  | 48 | MHz |  | 28 |
| 内部 APB 时钟频率 | fAPB-clock | 0 |  | 48 | MHz |  | 28 |
| I/O 输入电压范围 | VIO-range | -0.3 |  | 5.5 | V |  | 28 |
| VDD/VDDA 上升时间速率 | Tsupply-rise | 0 |  |  | μS/V |  | 28 |
| VDD/VDDA 下降时间速率 | Tsupply-fall | 20 |  |  | μS/V |  | 28 |
| VDD 上电复位阈值 | TVDD-POR | 1.84 | 1.92 | 2 | V |  | 28 |
| VDD 掉电复位阈值 | TVDD-fall | 1.8 | 1.88 | 1.96 | V |  | 28 |
| VDDA 掉电复位阈值 | TVDDA-fall | 1.8 | 1.88 | 1.96 | V |  | 28 |
| VVDD-range≤5.5V 的复位持续时间 | Treset-tempo |  | 4.2 | 10 | mS | VVDD-range≤5.5V | 28 |
| VVDD-range≤3.6V 的复位持续时间 | Treset-tempo |  | 4.2 | 7.5 | mS | VVDD-range≤3.6V | 28 |
| LVD 上升阈值电压 0 | VLVD | 2.11 | 2.18 | 2.25 | V |  | 28 |
| LVD 下降阈值电压 0 | VLVD | 2.01 | 2.08 | 2.15 | V |  | 28 |
| LVD 上升阈值电压 1 | VLVD | 2.2 | 2.28 | 2.36 | V |  | 28 |
| LVD 下降阈值电压 1 | VLVD | 2.1 | 2.18 | 2.26 | V |  | 28 |
| LVD 上升阈值电压 2 | VLVD | 2.29 | 2.38 | 2.47 | V |  | 28 |
| LVD 下降阈值电压 2 | VLVD | 2.19 | 2.28 | 2.37 | V |  | 28 |
| LVD 上升阈值电压 3 | VLVD | 2.39 | 2.48 | 2.57 | V |  | 28 |
| LVD 下降阈值电压 3 | VLVD | 2.29 | 2.38 | 2.47 | V |  | 28 |
| LVD 上升阈值电压 4 | VLVD | 2.48 | 2.58 | 2.68 | V |  | 28 |
| LVD 下降阈值电压 4 | VLVD | 2.38 | 2.48 | 2.58 | V |  | 28 |

## CAD (KiCad official)

- Symbol: `CS32F031K8S6-RA`
- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`
- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `cs32f031k8s6-ra-etched.step` / `cs32f031k8s6-ra-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cs32f031k8s6-ra.step` / `cs32f031k8s6-ra.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CHIPSEA datasheet](docs/cs32f031k8s6-ra-datasheet.pdf) (48 pp, sha256 `dbe20e12d3c88e3c`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cs32f031k8s6-ra-datasheet.pdf)