# CS32F030C8T6-RA

**CHIPSEA** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-48(7x7)

CS32F030C8T6-RA from CHIPSEA, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Pin 1 is marked NC (no connect) in the LQFP48 pin table. |
| 2 | PC13 | bidirectional | GPIO PC13 with RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2 functions. |
| 3 | PC14/LXT_IN | bidirectional | GPIO PC14, also the 32.768 kHz low-speed crystal oscillator input LXT_IN. |
| 4 | PC15/LXT_OUT | bidirectional | GPIO PC15, also the 32.768 kHz low-speed crystal oscillator output LXT_OUT. |
| 5 | PF0/HXT_IN | bidirectional | GPIO PF0, also the 4 to 32 MHz high-speed crystal oscillator input HXT_IN. |
| 6 | PF1/HXT_OUT | bidirectional | GPIO PF1, also the 4 to 32 MHz high-speed crystal oscillator output HXT_OUT. |
| 7 | NRST | bidirectional | Active-low reset input and internal reset output; after POR reset exit NRST must be held at least 9 ms or FWDT may be enabled. |
| 8 | GNDA | power_in | Analog ground. |
| 9 | VDDA | power_in | Analog power supply of 2.0 to 5.5 V; it must be above 2.4 V while the ADC operates and VDD-VDDA must not exceed 0.4 V. |
| 10 | PA0 | bidirectional | GPIO PA0 with USART2_CTS, ADC_IN0 and WKUP1 functions. |
| 11 | PA1 | bidirectional | GPIO PA1 with EVENTOUT, USART2_RTS and ADC_IN1 functions. |
| 12 | PA2 | bidirectional | GPIO PA2 with USART2_TX, TIM15_CH1 and ADC_IN2 functions. |
| 13 | PA3 | bidirectional | GPIO PA3 with USART2_RX, TIM15_CH2 and ADC_IN3 functions. |
| 14 | PA4 | bidirectional | GPIO PA4 with SPI1_NSS, USART2_CK, TIM14_CH1 and ADC_IN4 functions. |
| 15 | PA5 | bidirectional | GPIO PA5 with SPI1_SCK and ADC_IN5 functions. |
| 16 | PA6 | bidirectional | GPIO PA6 with SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT and ADC_IN6 functions. |
| 17 | PA7 | bidirectional | GPIO PA7 with SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT and ADC_IN7 functions. |
| 18 | PB0 | bidirectional | GPIO PB0 with TIM3_CH3, TIM1_CH2N, EVENTOUT and ADC_IN8 functions. |
| 19 | PB1 | bidirectional | GPIO PB1 with TIM3_CH4, TIM14_CH1, TIM1_CH3N and ADC_IN9 functions. |
| 20 | PB2 | bidirectional | GPIO PB2 with no alternate functions listed in the pin table. |
| 21 | PB10 | bidirectional | GPIO PB10 with I2C2_SCL function; I2C port supporting fast-mode plus. |
| 22 | PB11 | bidirectional | GPIO PB11 with EVENTOUT and I2C2_SDA functions; I2C port supporting fast-mode plus. |
| 23 | GND | power_in | Chip ground. |
| 24 | VDD | power_in | Digital power supply of 2.0 to 5.5 V for I/O, regulator and HXT. |
| 25 | PB12 | bidirectional | GPIO PB12 with TIM1_BKIN, EVENTOUT and SPI2_NSS functions. |
| 26 | PB13 | bidirectional | GPIO PB13 with TIM1_CH1N and SPI2_SCK functions. |
| 27 | PB14 | bidirectional | GPIO PB14 with TIM1_CH2N, TIM15_CH1 and SPI2_MISO functions. |
| 28 | PB15 | bidirectional | GPIO PB15 with TIM1_CH3N, TIM15_CH1N, TIM15_CH2, SPI2_MOSI and RTC_REFIN functions. |
| 29 | PA8 | bidirectional | GPIO PA8 with USART1_CK, TIM1_CH1, EVENTOUT and CKO functions. |
| 30 | PA9 | bidirectional | GPIO PA9 with USART1_TX, TIM1_CH2, I2C1_SCL and CKO functions; I2C port supporting fast-mode plus. |
| 31 | PA10 | bidirectional | GPIO PA10 with USART1_RX, TIM1_CH3, TIM17_BKIN and I2C1_SDA functions; I2C port supporting fast-mode plus. |
| 32 | PA11 | bidirectional | GPIO PA11 with USART1_CTS, TIM1_CH4 and EVENTOUT functions. |
| 33 | PA12 | bidirectional | GPIO PA12 with USART1_RTS, TIM1_ETR and EVENTOUT functions. |
| 34 | PA13 | bidirectional | GPIO PA13 multiplexed with SWDIO (internal pull-up active after reset when configured as SWDIO) and IR_OUT. |
| 35 | PF6 | bidirectional | GPIO PF6 with I2C2_SCL function; I2C port supporting fast-mode plus. |
| 36 | PF7 | bidirectional | GPIO PF7 with I2C2_SDA function; I2C port supporting fast-mode plus. |
| 37 | PA14 | bidirectional | GPIO PA14 multiplexed with SWCLK (internal pull-down active after reset when configured as SWCLK) and USART2_TX. |
| 38 | PA15 | bidirectional | GPIO PA15 with SPI1_NSS, USART2_RX and EVENTOUT functions; supports anti-backflow (input voltage above VDD allowed). |
| 39 | PB3 | bidirectional | GPIO PB3 with SPI1_SCK and EVENTOUT functions; supports anti-backflow (input voltage above VDD allowed). |
| 40 | PB4 | bidirectional | GPIO PB4 with SPI1_MISO, TIM3_CH1 and EVENTOUT functions; supports anti-backflow (input voltage above VDD allowed). |
| 41 | PB5 | bidirectional | GPIO PB5 with SPI1_MOSI, I2C1_SMBA, TIM16_BKIN and TIM3_CH2 functions; supports anti-backflow (input voltage above VDD allowed). |
| 42 | PB6 | bidirectional | GPIO PB6 with I2C1_SCL, USART1_TX and TIM16_CH1N functions; I2C port supporting fast-mode plus and anti-backflow. |
| 43 | PB7 | bidirectional | GPIO PB7 with I2C1_SDA, USART1_RX and TIM17_CH1N functions; I2C port supporting fast-mode plus and anti-backflow. |
| 44 | BOOT0 | input | Boot mode selection input; its low-level input voltage must not exceed 0.3*VDD-0.3 V. |
| 45 | PB8 | bidirectional | GPIO PB8 with I2C1_SCL and TIM16_CH1 functions; I2C port supporting fast-mode plus and anti-backflow. |
| 46 | PB9 | bidirectional | GPIO PB9 with I2C1_SDA, IR_OUT, TIM17_CH1 and EVENTOUT functions; I2C port supporting fast-mode plus and anti-backflow. |
| 47 | GND | power_in | Chip ground. |
| 48 | VDD | power_in | Digital power supply of 2.0 to 5.5 V for I/O, regulator and HXT. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | CHIPSEA |
| Package | LQFP-48(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD 和 GND 之间的电压 | VDD | -0.3 |  | 6 | V |  | 28 |
| VDDA 和 GND 之间的电压 | VDDA | -0.3 |  | 6 | V |  | 28 |
| VDD 和 VDDA 之间的电压 | VDD-VDDA |  |  | 0.4 | V |  | 28 |
| I/O 管脚电压 | Vi/o |  |  | 6 | V |  | 28 |
| 存储温度 | Tstorage | -65 |  | 150 | ℃ |  | 28 |
| 结温 | Tjunction |  |  | 150 | ℃ |  | 28 |
| 流入 VDD 电源线的总电流 | Itotal-pwr |  |  | 120 | mA |  | 28 |
| 流出 GND 接地线的总电流 | Itotal-GND | -120 |  |  | mA |  | 28 |
| 流入每个电源管脚的电流 | Ipwr-pin |  |  | 100 | mA |  | 28 |
| 流入每个地管脚的电流 | IGND-pin | -100 |  |  | mA |  | 28 |
| 流入所有 I/O 管脚的总电流 | Itotal-sunk |  |  | 80 | mA |  | 28 |
| 流出所有 I/O 管脚的总电流 | Itotal-source | -80 |  |  | mA |  | 28 |
| 流入任意一个 I/O 管脚的电流 | Isunk-pin |  |  | 25 | mA |  | 28 |
| 流出任意一个 I/O 管脚的总电流 | Isource-pin | -25 |  |  | mA |  | 28 |
| VDD 的工作电压范围 | VVDD-range | 2 |  | 5.5 | V |  | 28 |
| VDDA 的工作电压范围 | VVDDA-range | 2 |  | 5.5 | V |  | 28 |
| 芯片环境温度 | Trange | -40 |  | 85 | ℃ |  | 28 |
| 芯片结温范围 | Tjunction-range | -40 |  | 125 | ℃ |  | 28 |
| 内部 AHB 时钟频率 | fAHB-clock | 0 |  | 48 | MHz |  | 28 |
| 内部 APB 时钟频率 | fAPB-clock | 0 |  | 48 | MHz |  | 28 |
| I/O 输入电压范围 | VIO-range | -0.3 |  | 5.5 | V |  | 28 |
| VDD/VDDA 上升时间速率 | Tsupply-rise | 0 |  |  | μS/V |  | 28 |
| VDD/VDDA 下降时间速率 | Tsupply-fall | 20 |  |  | μS/V |  | 28 |
| VDD 上电复位阈值 | TVDD-POR | 1.84 | 1.92 | 2 | V |  | 28 |
| VDD 掉电复位阈值 | TVDD-fall | 1.8 | 1.88 | 1.96 | V |  | 28 |
| VDDA 掉电复位阈值 | TVDDA-fall | 1.8 | 1.88 | 1.96 | V |  | 28 |
| 复位持续时间 | Treset-tempo |  | 4.2 | 10 | mS | VVDD-range≤5.5V | 28 |
| 复位持续时间 | Treset-tempo |  | 4.2 | 7.5 | mS | VVDD-range≤3.6V | 28 |
| LVD 上升阈值电压 0 | VLVD | 2.11 | 2.18 | 2.25 | V |  | 28 |
| LVD 下降阈值电压 0 | VLVD | 2.01 | 2.08 | 2.15 | V |  | 28 |
| LVD 上升阈值电压 1 | VLVD | 2.2 | 2.28 | 2.36 | V |  | 28 |
| LVD 下降阈值电压 1 | VLVD | 2.1 | 2.18 | 2.26 | V |  | 28 |
| LVD 上升阈值电压 2 | VLVD | 2.29 | 2.38 | 2.47 | V |  | 28 |
| LVD 下降阈值电压 2 | VLVD | 2.19 | 2.28 | 2.37 | V |  | 28 |
| LVD 上升阈值电压 3 | VLVD | 2.39 | 2.48 | 2.57 | V |  | 28 |
| LVD 下降阈值电压 3 | VLVD | 2.29 | 2.38 | 2.47 | V |  | 28 |
| LVD 上升阈值电压 4 | VLVD | 2.48 | 2.58 | 2.68 | V |  | 28 |
| LVD 下降阈值电压 4 | VLVD | 2.38 | 2.48 | 2.58 | V |  | 28 |

## CAD (KiCad official)

- Symbol: `CS32F030C8T6-RA`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `cs32f030c8t6-ra-etched.step` / `cs32f030c8t6-ra-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cs32f030c8t6-ra.step` / `cs32f030c8t6-ra.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [CHIPSEA datasheet](docs/cs32f030c8t6-ra-datasheet.pdf) (48 pp, sha256 `dbe20e12d3c88e3c`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cs32f030c8t6-ra-datasheet.pdf)