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CS32A039R8T6

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CHIPSEA Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CS32A039R8T6

CHIPSEA · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(7x7)

CS32A039R8T6 from CHIPSEA, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA3 bidirectional General-purpose I/O port PA3 with alternate functions per Table 3 including TIM15_CH2, USART1_RX, TIM2_CH4 and USART2_RX.
2 PA4 bidirectional General-purpose I/O port PA4 with alternate functions per Table 3 including SPI1_NSS, I2S1_WS, USART1_CK and TIM14_CH1.
3 PA5 bidirectional General-purpose I/O port PA5 with alternate functions per Table 3 including SPI1_SCK, I2S1_CK, TIM2_CH1_ETR and USART7_TX.
4 PA6 bidirectional General-purpose I/O port PA6 with alternate functions per Table 3 including SPI1_MISO, I2S1_MCK, TIM3_CH1 and TIM1_BKIN.
5 PA7 bidirectional General-purpose I/O port PA7 with alternate functions per Table 3 including SPI1_MOSI, I2S1_SD, TIM3_CH2 and TIM1_CH1N.
6 PB0 bidirectional General-purpose I/O port PB0 with alternate functions per Table 4 including EVENTOUT, TIM3_CH3 and TIM1_CH2N.
7 PB1 bidirectional General-purpose I/O port PB1 with alternate functions per Table 4 including TIM14_CH1, TIM3_CH4 and TIM1_CH3N.
8 PB2 bidirectional General-purpose I/O port PB2; no alternate function is listed for PB2 in Table 4 of this extract.
9 PB10 bidirectional General-purpose I/O port PB10 with alternate functions per Table 4 including I2C1_SCL, TIM2_CH3 and I2C2_SCL.
10 PB11 bidirectional General-purpose I/O port PB11 with alternate functions per Table 4 including EVENTOUT, I2C1_SDA, TIM2_CH4 and I2C2_SDA.
11 GND power_in Chip ground, including digital and analog ground.
12 ADC2_SCLK input Sigma-Delta ADC (ADC2) serial communication clock port.
13 ADC2_SDA bidirectional Sigma-Delta ADC (ADC2) serial communication data port.
14 ADC2_VDD power_in Sigma-Delta ADC (ADC2) digital power supply.
15 ADC2_VDDA power_in Sigma-Delta ADC (ADC2) analog power supply.
16 ADC2_GNDA power_in Sigma-Delta ADC (ADC2) ground.
17 ADC2_VS power_out Sigma-Delta ADC (ADC2) LDO output port, selectable 2.35 V / 2.45 V / 2.8 V / 3.0 V and rated up to 10 mA load per Section 7.8.4.
18 ADC2_REFP input Sigma-Delta ADC (ADC2) positive reference voltage input port.
19 ADC2_REFN input Sigma-Delta ADC (ADC2) negative reference voltage input port.
20 ADC2_AIN0 input Sigma-Delta ADC (ADC2) analog signal input channel 0, usable in differential or single-ended mode per Section 5.1.
21 ADC2_AIN1 input Sigma-Delta ADC (ADC2) analog signal input channel 1, usable in differential or single-ended mode per Section 5.1.
22 ADC2_AIN2 input Sigma-Delta ADC (ADC2) analog signal input channel 2, usable in differential or single-ended mode per Section 5.1.
23 ADC2_AIN3 input Sigma-Delta ADC (ADC2) analog signal input channel 3, usable in differential or single-ended mode per Section 5.1.
24 ADC2_AIN4 input Sigma-Delta ADC (ADC2) analog signal input channel 4, usable in differential or single-ended mode per Section 5.1.
25 ADC2_CIP passive Sigma-Delta ADC (ADC2) analog filter port, positive filter-capacitor output and input, used with an external filter capacitor per Section 7.8.3.
26 ADC2_CIN passive Sigma-Delta ADC (ADC2) analog filter port, negative filter-capacitor output and input, used with an external filter capacitor per Section 7.8.3.
27 ADC2_CS input Sigma-Delta ADC (ADC2) chip-select port, also used as programming voltage VPP per Table 2.
28 VDD power_in Digital power supply, rated 2.0 V to 3.6 V per Table 18.
29 PB12 bidirectional General-purpose I/O port PB12 with alternate functions per Table 4 including SPI1_NSS, EVENTOUT, TIM1_BKIN and SPI2_NSS.
30 PB13 bidirectional General-purpose I/O port PB13 with alternate functions per Table 4 including SPI1_SCK, TIM1_CH1N and SPI2_SCK.
31 PB14 bidirectional General-purpose I/O port PB14 with alternate functions per Table 4 including SPI1_MISO, TIM15_CH1, TIM1_CH2N and SPI2_MISO.
32 PB15 bidirectional General-purpose I/O port PB15 with alternate functions per Table 4 including SPI1_MOSI, TIM15_CH2, TIM1_CH3N and SPI2_MOSI.
33 PA8 bidirectional General-purpose I/O port PA8 with alternate functions per Table 3 including CKO, USART1_CK, TIM1_CH1 and EVENTOUT.
34 PA9 bidirectional General-purpose I/O port PA9 with alternate functions per Table 3 including TIM15_BKIN, USART1_TX, TIM1_CH2 and I2C1_SCL.
35 PA10 bidirectional General-purpose I/O port PA10 with alternate functions per Table 3 including TIM17_BKIN, USART1_RX, TIM1_CH3 and I2C1_SDA.
36 PA11 bidirectional General-purpose I/O port PA11 with alternate functions per Table 3 including EVENTOUT, USART1_CTS and TIM1_CH4.
37 PA12 bidirectional General-purpose I/O port PA12 with alternate functions per Table 3 including EVENTOUT, USART1_RTS and TIM1_ETR.
38 PA13 bidirectional General-purpose I/O port PA13 multiplexed with SWDIO (serial wire debug data) per Table 2 and Table 3, with IR_OUT and USART6_RX/USART7_RX/USART8_RX as alternates.
39 PF6 bidirectional General-purpose I/O port PF6; no alternate function is listed for PF6 in the Section 5 tables of this extract.
40 PF7 bidirectional General-purpose I/O port PF7; no alternate function is listed for PF7 in the Section 5 tables of this extract.
41 PA14 bidirectional General-purpose I/O port PA14 multiplexed with SWCLK (serial wire debug clock) per Table 2 and Table 3, with USART1_TX, USART6_TX, USART7_TX, USART8_TX and USART2_TX as alternates.
42 PA15 bidirectional General-purpose I/O port PA15 with alternate functions per Table 3 including SPI1_NSS, I2S1_WS, USART1_RX, TIM2_CH1_ETR and EVENTOUT.
43 PB3 bidirectional General-purpose I/O port PB3 with alternate functions per Table 4 including SPI1_SCK, I2S1_CK, EVENTOUT and TIM2_CH2.
44 PB4 bidirectional General-purpose I/O port PB4 with alternate functions per Table 4 including SPI1_MISO, I2S1_MCK, TIM3_CH1 and EVENTOUT.
45 PB5 bidirectional General-purpose I/O port PB5 with alternate functions per Table 4 including SPI1_MOSI, I2S1_SD, TIM3_CH2, TIM16_BKIN and I2C1_SMBA.
46 PB6 bidirectional General-purpose I/O port PB6 with alternate functions per Table 4 including USART1_TX, I2C1_SCL, TIM16_CH1N and USART6_TX.
47 PB7 bidirectional General-purpose I/O port PB7 with alternate functions per Table 4 including USART1_RX, I2C1_SDA, TIM17_CH1N and USART6_RX.
48 BOOT0 input Boot memory selection pin; its level, together with nBOOT1, selects the boot location per Table 6.
49 PB8 bidirectional General-purpose I/O port PB8 with alternate functions per Table 4 including I2C1_SCL and TIM16_CH1.
50 PB9 bidirectional General-purpose I/O port PB9 with alternate functions per Table 4 including IR_OUT, I2C1_SDA, TIM17_CH1 and EVENTOUT.
51 GND power_in Chip ground.
52 VDD power_in Digital power supply, rated 2.0 V to 3.6 V per Table 18.
53 VBAT power_in Backup power supply for RTC, LXT and backup registers, rated 1.65 V to 3.6 V per Section 7.4.1.
54 PC13 bidirectional General-purpose I/O port PC13 with alternate functions RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2 per Table 2.
55 PC14/LXT_IN passive Low-speed crystal (LXT) input, 32.768 kHz, also general-purpose port PC14 per Table 2.
56 PC15/LXT_OUT passive Low-speed crystal (LXT) output, also general-purpose port PC15 per Table 2.
57 PF0/HXT_IN passive High-speed crystal (HXT) input, 4 to 32 MHz per Figure 5, also general-purpose port PF0 per Table 2.
58 PF1/HXT_OUT passive High-speed crystal (HXT) output, also general-purpose port PF1 per Table 2.
59 NRST bidirectional Reset input and internal reset output, active low, per Table 2.
60 GNDA power_in Analog ground.
61 VDDA power_in Analog power supply for ADC, HRC, HRC14, PLL, POR/PDR and LVD, ranging from VDD to 3.6 V per Section 7.4.1.
62 PA0 bidirectional General-purpose I/O port PA0 with alternate functions per Table 3 including USART1_CTS, TIM2_CH1_ETR and USART2_CTS.
63 PA1 bidirectional General-purpose I/O port PA1 with alternate functions per Table 3 including EVENTOUT, USART1_RTS, TIM2_CH2 and USART2_RTS.
64 PA2 bidirectional General-purpose I/O port PA2 with alternate functions per Table 3 including TIM15_CH1, USART1_TX, TIM2_CH3 and USART2_TX.

Key specifications

Parameter Value
Manufacturer CHIPSEA
Package LQFP-64(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Data Rate 10 40 1280 SPS 29
Offset error -8 8 uV Gain=128 29
Offset error -100 100 uV Gain=1 30
Offset error drift -0.5 0.5 nv/℃ Gain=128 30
VS voltage VS 2.35 2.45 2.6 V LDOS[1:0]=01 30
VREF voltage VREF 1.197 1.225 1.239 V 30
Power supply voltage VDD 2.4 3 3.6 V 30

CAD (KiCad official)

  • Symbol: CS32A039R8T6
  • Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
  • 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
  • 3D model files: cs32a039r8t6-etched.step / cs32a039r8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cs32a039r8t6.step / cs32a039r8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CHIPSEA datasheet (52 pp, sha256 b8cbf1264cfea562, retrieved 2026-10-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF